DAC8420_07 Datasheet, PDF (14/24 Pages) Analog Devices – Quad 12-Bit Serial Voltage Output DAC

DAC8420
THEORY OF OPERATION
INTRODUCTION
The DAC8420 is a quad, voltage-output 12-bit DAC with a serial
digital input capable of operating from a single 5 V supply. The
straightforward serial interface can be connected directly to
most popular microprocessors and microcontrollers, and can
accept data at a 10 MHz clock rate when operating from ±15 V
supplies. A unique voltage reference structure ensures maximum
utilization of the DAC output resolution by allowing the user to
set the zero-scale and full-scale output levels within the supply
rails. The analog voltage outputs are fully buffered, and are
capable of driving a 2 kΩ load. Output glitch impulse during
major code transitions is a very low 64 nV-s (typ).
DIGITAL INTERFACE OPERATION
The serial input of the DAC8420, consisting of CS, SDI, and
LD, is easily interfaced to a wide variety of microprocessor serial
ports. While CS is low, the data presented to the input SDI is
shifted into the internal serial-to-parallel shift register on the
rising edge of the clock, with the address MSB first, data LSB
last, as shown in Table 6 and in the timing diagram (Figure 2).
The data format, shown in Table 8, is two bits of DAC address
and two don’t care fill bits, followed by the 12-bit DAC data-
word. Once all 16 bits of the serial data-word have been input,
the load control LD is strobed and the word is parallel-shifted
out onto the internal data bus. The two address bits are decoded
and used to route the 12-bit data-word to the appropriate DAC
data register (see the Applications section).
CORRECT OPERATION OF CS AND CLK
In Table 6, the control pins CLK and CS require some attention
during a data load cycle. Since these two inputs are fed to the
same logical OR gate, the operation is in fact identical. The user
must take care to operate them accordingly to avoid clocking in
false data bits. In the timing diagram, CLK must be halted high
or CS must be brought high during the last high portion of the
CLK following the rising edge that latched in the last data bit.
Otherwise, an additional rising edge is generated by CS rising
while CLK is low, causing CS to act as the clock and allowing a
false data bit into the serial input register. The same issue must
also be considered in the beginning of the data load sequence.
Table 8.
(FIRST)
B0 B1 B2 B3
B4
B5
B6 B7
A1 A0 NC NC D11 D10 D9 D8
—Address Word—
(MSB)
USING CLR AND CLSEL
The clear (CLR) control allows the user to perform an asyn-
chronous reset function. Asserting CLR loads all four DAC
data-word registers, forcing the DAC outputs to either zero
scale (0x000) or midscale (0x800), depending on the state of
CLSEL as shown in Table 6. The clear function is asynchronous
and totally independent of CS. When CLR returns high, the
DAC outputs remain latched at the reset value until LD is
strobed, reloading the individual DAC data-word registers
with either the data held in the serial input register prior to the
reset or with new data loaded through the serial interface.
Table 7. DAC Address Word Decode Table
A1
A0
DAC Addressed
0
0
DAC A
0
1
DAC B
1
0
DAC C
1
1
DAC D
PROGRAMMING THE ANALOG OUTPUTS
The unique differential reference structure of the DAC8420
allows the user to tailor the output voltage range precisely to
the needs of the application. Instead of spending DAC resolu-
tion on an unused region near the positive or negative rail, the
DAC8420 allows the user to determine both the upper and
lower limits of the analog output voltage range. Thus, as shown
in Table 9 and Figure 30, the outputs of DAC A through DAC D
range between VREFHI and VREFLO, within the limits specified
in the Specifications section. Note also that VREFHI must be
greater than VREFLO.
V_DD
V_VREFHI
2.5V MIN
0xFFF
2.5V MIN
1 LSB
V_VREFLO
0x000
–10V MIN
0V MIN
V_SS
Figure 30. Output Voltage Range Programming
(LAST)
B8 B9 B10 B11 B12 B13 B14 B15
D7 D6 D5 D4 D3 D2 D1 D0
—DAC Data-Word—
(LSB)
Rev. B | Page 14 of 24