DAC8420_07 Datasheet, PDF (17/24 Pages) Analog Devices – Quad 12-Bit Serial Voltage Output DAC

DAC8420
APPLICATIONS
POWER SUPPLY BYPASSING AND GROUNDING
In any circuit where accuracy is important, careful consid-
eration of the power supply and ground return layout helps
to ensure the rated performance. The DAC8420 has a single
ground pin that is internally connected to the digital section
as the logic reference level. The first thought may be to connect
this pin to digital ground; however, in large systems digital
ground is often noisy because of the switching currents of other
digital circuitry. Any noise that is introduced at the ground pin
can couple into the analog output. Thus, to avoid error-causing
digital noise in the sensitive analog circuitry, the ground pin
should be connected to the system analog ground. The ground
path (circuit board trace) should be as wide as possible to reduce
any effects of parasitic inductance and ohmic drops. A ground
plane is recommended if possible. The noise immunity of the
on-board digital circuitry, typically in the hundreds of milli-
volts, is well able to reject the common-mode noise typically
seen between system analog and digital grounds. Finally, the
analog and digital ground should be connected to each other
at a single point in the system to provide a common reference.
This is preferably done at the power supply.
performance of the device, the supply should be as noise free as
possible. In the case of 5 V only systems, it is desirable to use
the same 5 V supply for both the analog circuitry and the
digital portion of the circuit. Unfortunately, the typical 5 V
supply is extremely noisy due to the fast edge rates of the
popular CMOS logic families, which induce large inductive
voltage spikes, and busy microcontroller or microprocessor
buses, and therefore commonly have large current spikes during
bus activity. However, by properly filtering the supply as shown
in Figure 32, the digital 5 V supply can be used. The inductors
and capacitors generate a filter that not only rejects noise due
to the digital circuitry, but also filters out the lower frequency
noise of switch mode power supplies. The analog supply should
be connected as close as possible to the origin of the digital
supply to minimize noise pickup from the digital section.
TTL/CMOS
LOGIC
CIRCUITS
FERRITE BEADS:
2 TURNS, FAIR-RITE
#2677006301
+ _100µF +10µF _{TO 22µF}
ELECT. TANT.
+5V
0.1µF
CER.
+5V
RETURN
Good grounding practice is also essential to maintaining analog
performance in the surrounding analog support circuitry. With
two reference inputs and four analog outputs capable of moderate
bandwidth and output current, there is a significant potential
for ground loops. Again, a ground plane is recommended as the
most effective solution to minimizing errors due to noise and
ground offsets.
+V_S
10µF
0.1µF
1 _VDD
–V_S
8
V_SS
10µF 0.1µF
9
GND
10µF = TANTALUM
0.1µF = CERAMIC
Figure 31. Recommended Supply Bypassing Scheme
The DAC8420 should have ample supply bypassing, located as
close to the package as possible. Figure 31 shows the recom-
mended capacitor values of 10 μF in parallel with 0.1 μF. The
0.1 μF capacitor should have low effective series resistance (ESR)
and effective series inductance (ESI) (such as any common
ceramic type capacitor), which provide a low impedance path
to ground at high frequencies to handle transient currents due
to internal logic switching. To preserve the specified analog
+5V
POWER SUPPLY
Figure 32. Single-Supply Analog Supply Filter
ANALOG OUTPUTS
The DAC8420 features buffered analog voltage outputs capable
of sourcing and sinking up to 5 mA when operating from ±15 V
supplies, eliminating the need for external buffer amplifiers in
most applications while maintaining specified accuracy over the
rated operating conditions. The buffered outputs are simply an
op amp connected as a voltage follower, and thus have output
characteristics very similar to the typical operational amplifier.
These amplifiers are short-circuit protected. The user should
verify that the output load meets the capabilities of the device,
in terms of both output current and load capacitance. The
DAC8420 is stable with capacitive loads up to 2 nF typically.
However, any capacitive load will increase the settling time,
and should be minimized if speed is a concern.
The output stage includes a P-channel MOSFET to pull the
output voltage down to the negative supply. This is very important
in single-supply systems where VREFLO usually has the same
potential as the negative supply. With no load, the zero-scale
output voltage in these applications is less than 500 μV typically,
or less than 1 LSB when VVREFHI = 2.5 V. However, when sinking
current, this voltage does increase because of the finite imped-
ance of the output stage. The effective value of the pull-down
resistor in the output stage is typically 320 Ω. With a 100 kΩ
resistor connected to 5 V, the resulting zero-scale output voltage
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