PAC5253_17 Datasheet, PDF (52/71 Pages) Active-Semi, Inc – Power Application Controller

PAC5253
Power Application Controller
16. ARM CORTEX-M0 MICROCONTROLLER CORE
16.1. Features
 ARM Cortex-M0 core
 Fast single-cycle 32-bit x 32-bit multiplier
 24-bit SysTick timer
 Up to 50MHz operation
 Serial wire debug (SWD), with 4 break-point and 2 watch-point unit comparators
 Nested vectored interrupt controller (NVIC) with 25 external interrupts
 Wake-up interrupt controller (WIC) with GPIO, real-time clock (RTC) and watchdog timer (WDT) interrupts
enabled
 Sleep and deep-sleep mode with clock gating
16.2. Block Diagram
Figure 16-1. ARM Cortex-M0 Microcontroller Core
ARM CORTEX-M0 MICROCONTROLLER CORE
SWDCL
SWDDA
SERIAL WIRE
DEBUG WITH
DISABLE
ARM
CORTEX-M0
1-CYCLE
32X32
MULTIPLIER
24-BIT
SYSTICK
NESTED
VECTORED
INTERRUPT
CONTROLLER
WAKE-UP
INTERRUPT
CONTROLLER
16.3. Functional Description
The ARM Cortex-M0 microcontroller core is configured for little endian operation and includes the fast single-cycle 32-bit
multiplier and 24-bit SysTick timer and can operate at a frequency of up to 50MHz.
The microcontroller nested vectored interrupt controller (NVIC) supports 25 external interrupts for the device's peripherals
and sub-systems. For low-latency interrupt processing, the NVIC also supports interrupt tail-chaining. The wake-up
interrupt controller (WIC) is able to wake up the device from low-power modes using any GPIO interrupt, as well as from
the RTC or WDT. The ARM Cortex-M0 supports both sleep and deep-sleep low-power modes. The deep-sleep mode
supports clock gating to limit standby power even further.
Firmware debug support includes 4 break-point and 2 watch-point unit comparators using the serial wire debug (SWD)
protocol. The serial wire debug mechanism can be disabled to prevent device access to the firmware in the field.
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Rev 1.18‒December 29, 2016