PAC5253_17 Datasheet, PDF (40/71 Pages) Active-Semi, Inc – Power Application Controller

PAC5253
Power Application Controller
Figure 12-3. High-Side Switching Transients and Optional Circuitry
V ≤ 625V
DXBx
DXBx
DXHx
DXSx
V
P
V
IN
V
DXBx
dV/dt
dV/dt
V
DXSx
V ≥ -10V
DXSx
(a) High-Side Switching Transients
PAC5253
DRLx
(b) Optional Transient Protection and Slew Rate Control
12.3.4. Power Drivers Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers controlled by the microcontroller ports and PWM signals according to Table 21,
with configurable delays as shown in Table 21. Refer to the PAC application notes and user guide for additional
information on power drivers control programming.
Table 21. Microcontroller Port and PWM to Power Driver Mapping
PART
NUMBER
PWMA0
PWMA1
PWMA2
PWMA3/
PWMA4/
PWMB0
PAC5253
DRL0
DRL1
DRL2
DRL3
PWMA4/
PWMB0
DXH0
PWMA5/
PWMA7/
PWMC1
DXH1
PWMA6/
PWMD0
DXH2
Table 22. Power Driver Delay Configuration
DELAY
SETTING
RISING
DRLx
Default Setting
130ns
01b Setting
170ns
10b Setting
230ns
11b Setting
360ns
FALLING
140ns
180ns
250ns
380ns
RISING
200ns
DXHx
FALLING
240ns
12.3.5. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using two protection event signals from the
Configurable Analog Front End (CAFE), designated as protection event 1 (PR1) and protection event 2 (PR2) signals. The
DRL0/DRL1/DRL2 drivers are designated as low-side group 1, and the DRL3 gate driver are designed as low-side group 2.
The DXH0/DXH1/DXH2 ultra-high-voltage gate drivers are designated as high-side group 1. The PR1 signal from the
CAFE can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit settings. The PR2
signal from the CAFE can be used to disable low-side group 2, high-side group 2, or both depending on the PR2 mask bit
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Rev 1.18‒December 29, 2016