PAC5253_17 Datasheet, PDF (29/71 Pages) Active-Semi, Inc – Power Application Controller

PAC5253
Power Application Controller
11.2. Functional Description
The device includes a Configurable Analog Front End (CAFE, Figure 11-1) accessible through up to 10 analog and I/O
pins. These pins can be configured to form flexible interconnected circuitry made up of up to 3 differential programmable
gain amplifiers, 4 single-ended programmable gain amplifiers, 4 general purpose comparators, 3 phase comparators, 10
protection comparators, and one buffer output. These pins can also be programmed as analog feed-through pins, or as
analog front end I/O pins that can function as digital inputs or digital open-drain outputs. The PAC proprietary configurable
analog signal matrix (CASM) and configurable digital signal matrix (CDSM) allow real time asynchronous analog and
digital signals to be routed in flexible circuit connections for different applications. A push button function is provided for
optional push button on, hibernate, and off power management function.
11.2.1. Differential Programmable Gain Amplifier (DA)
The DAxP and DAxN pin pair are positive and negative inputs, respectively, to a differential programmable gain amplifier.
The differential gain can be programmable to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x for zero ohm signal source impedance.
The differential programmable gain amplifier has -0.3V to 3.5V input common mode range, and its output can be
configured for routing directly to the ADC pre-multiplexer, or through a sample-and-hold circuit synchronized with the
ADC auto-sampling mechanism. Each differential amplifier is accompanied by offset calibration circuitry, and two
protection comparators for protection event monitoring. The programmable gain differential amplifier is optimized for use
with signal source impedance lower than 500Ω and with matched source impedance on both positive and negative
inputs for minimal offset. The effective gain is scaled by 13.5k / (13.5k + RSOURCE), where RSOURCE is the matched
source impedance of each input.
11.2.2. Single-Ended Programmable Gain Amplifier (AMP)
Each AMPx input goes to a single-ended programmable gain amplifier with signal relative to VSSA. The amplifier gain can
be programmed to be 1x, 2x, 4x, 8x, 16x, 32x, and 48x, or as analog feed-through. The programmable gain amplifier output
is routed via a multiplexer to the configurable analog signal matrix CASM.
11.2.3. General Purpose Comparator (CMP)
The general purpose comparator takes the CMPx input and compares it to either the programmable threshold voltage
(VTHREF) or a signal from the configurable analog signal matrix CASM. The comparator has 0V to VSYS input common mode
range, and its polarity-selectable output is routed via a multiplexer to either a data input bit or the configurable digital signal
matrix CDSM. Each general purpose comparator has two mask bits to prevent or allow rising or falling edge of its output to
trigger second microcontroller interrupt INT2, where INT2 can be configured to activate protection event PR1. Each
comparator output, routed via CASM and with 500ns de-glitch time, can also be configured to activate protection event
PR1.
11.2.4. Phase Comparator (PHC)
The phase comparator takes the PHCx input and compares it to either the programmable threshold voltage (V ) THREF or a
signal from the configurable analog signal matrix CASM. The comparison signal can be set to a phase reference signal
generated by averaging the PHCx input voltages. In a three-phase motor control application, the phase reference signal acts
as a virtual center tap for BEMF detection. The PHCx inputs are optionally fed through to the CASM. The phase
comparator has 0V to VSYS input common mode range, and its polarity-selectable output is routed to a data input bit and to
the phase/position multiplexer synchronized with the auto-sampling sequencers.
11.2.5. Protection Comparator (PCMP)
Two protection comparators are provided in association with each differential programmable gain amplifier, with outputs
available to trigger protection events and accessible as read-back output bits. The high-speed protection (HP) comparator
compares the PCMPx pin to the 8-bit HP DAC output voltage, with full scale voltage of 2.5V. The limit protection (LP)
comparator compares the differential programmable gain amplifier output to the 10-bit LP DAC output voltage, with full
scale voltage of 2.5V.
Each protection comparator has a mask bit to prevent or allow it to trigger the main microcontroller interrupt INT1. Each
protection comparator also has one mask bit to prevent or allow it to activate protection event PR1, and another mask bit to
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Rev 1.18‒December 29, 2016