PAC5223 Datasheet, PDF (40/67 Pages) Active-Semi, Inc – Power Application Controller

PAC5223
Power Application Controller
Figure 12-3. High-Side Switching Transients and Optional Circuitry
V ≤ 83V
DRBx
DRBx
DRHx
V
P
V
IN
DRSx
V
DRBx
dV/dt
dV/dt
PAC5223
DRLx
V
DRSx
V ≥ -5V
DRSx
(a) High-Side Switching Transients
12.3.4. Power Drivers Control
(b) Optional Transient Protection and Slew Rate Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers are controlled by the microcontroller ports and/or PWM signals according to
Table 23, with configurable delays as shown in Table 24. The OHIx open-drain drivers are controlled by their
corresponding register bits. Refer to the PAC application notes and user guide for additional information on power drivers
control programming.
Table 23. Microcontroller Port and PWM to Power Driver Mapping
PART
NUMBER
PWMA0
PWMA1
PWMA2
PWMA3/
PWMA4/
PWMB0
PAC5223
DRL0
DRL1
DRL2
DRH3
PWMA5/
PWMC0
DRH4
PWMA6/
PWMD0
DRH5
Table 24. Power Driver Delay Configuration
DELAY
SETTING
RISING
DRLx
00b Default Setting
130ns
01b Setting
170ns
10b Setting
230ns
11b Setting
360ns
FALLING
140ns
180ns
250ns
380ns
RISING
160ns
200ns
260ns
380ns
DRHx
FALLING
140ns
180ns
240ns
370ns
12.3.5. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using protection signal from the Configurable Analog
Front End (CAFE), designated as protection event 1 (PR1) signal. The DRL0/DRL1/DRL2 drivers are designated as low-
side group 1. The DRH3/DRH4/DRH5 gate drivers are designated as high-side group 1. The PR1 signal from the CAFE
can be used to disable low-side group 1, high-side group 1, or both depending on the PR1 mask bit settings.
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Rev 1.10‒January 28, 2016