AX1000-1FGG896I Datasheet, PDF (76/226 Pages) Actel Corporation – Axcelerator Family FPGAs

Axcelerator Family FPGAs
Implementation Example:
Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from
non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2
output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both
CLKF and CLKG global resources.
HCLKAP
HCLKAN
RefCLK
CLK1
PLLA
FB
CLK2
Figure 2-45 • Example of HCLKA driven from a PLL with External Clock Source
PLLHCLK
HCLKA
Network
PLLINT
Logic
RefCLK CLK1
PLLA
FB
CLK2
PLLHCLK
HCLKA
Network
Figure 2-46 • Example of PLLINT and PLLOUT Usage
Non-Clock
Pins
INBUF
P
N
PLLINT
PLLRCLK
RefCLK CLK1
PLLE
FB
CLK2
PLLOUT
PLLOUT
Logic
Logic
CLKINT
CLKE
RefCLK CLK1
PLLF
FB
CLK2
Figure 2-47 • Complex Clock Distribution Example
PLLRCLK
CLKF
CLKG
PLLRCLK
2-62
v2.7