AX1000-1FGG896I Datasheet, PDF (101/226 Pages) Actel Corporation – Axcelerator Family FPGAs

Axcelerator Family FPGAs
Table 2-98 • Two FIFO Blocks Cascaded
Worst-Case Commercial Conditions V_CCA = 1.425V, V_CCI = 3.0V, T_J = 70°C
'–2' Speed
'–1' Speed
Parameter
Description
Min. Max. Min. Max.
FIFO Module Timing
t_WSU
t_WHD
t_WCKH
t_WCKL
t_WCKP
t_RSU
t_RHD
t_RCKH
t_RCKL
t_RCKP
t_CLRHF
t_CLR2FF
t_CLR2AF
t_CK2FF
t_CK2AF
t_RCK2RD1
t_RCK2RD2
Write Setup
Write Hold
WCLK High
WCLK Low
Minimum WCLK Period
Read Setup
Read Hold
RCLK High
RCLK Low
Minimum RCLK period
Clear High
Clear-to-flag (EMPTY/FULL)
Clear-to-flag (AEMPTY/AFULL)
Clock-to-flag (EMPTY/FULL)
Clock-to-flag (AEMPTY/AFULL)
RCLK-To-OUT (Pipelined)
RCLK-To-OUT (Nonpipelined)
1.39
1.59
0.22
0.25
0.98
1.11
2.29
2.61
4.58
5.22
1.7
1.94
0
0
0.95
1.08
2.46
2.8
4.92
5.6
1.08
1.23
2.02
2.3
4.62
5.26
2.24
2.55
5.31
6.05
1.51
1.72
2.76
3.14
'Std' Speed
Min. Max.
1.86
0.3
1.31
3.07
6.14
2.28
0
1.27
3.29
6.58
1.45
2.7
6.19
3
7.11
2.02
3.69
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 2-99 • Four FIFO Blocks Cascaded
Worst-Case Commercial Conditions V_CCA = 1.425V, V_CCI = 3.0V, T_J = 70°C
'–2' Speed
'–1' Speed
Parameter
Description
Min. Max. Min. Max.
FIFO Module Timing
t_WSU
t_WHD
t_WCKH
t_WCKL
t_WCKP
t_RSU
t_RHD
t_RCKH
t_RCKL
t_RCKP
t_CLRHF
t_CLR2FF
t_CLR2AF
t_CK2FF
t_CK2AF
t_RCK2RD1
t_RCK2RD2
Write Setup
Write Hold
WCLK High
WCLK Low
Minimum WCLK Period
Read Setup
Read Hold
RCLK High
RCLK Low
Minimum RCLK period
Clear High
Clear-to-flag (EMPTY/FULL)
Clear-to-flag (AEMPTY/AFULL)
Clock-to-flag (EMPTY/FULL)
Clock-to-flag (AEMPTY/AFULL)
RCLK-To-OUT (Pipelined)
RCLK-To-OUT (Nonpipelined)
2.37
2.7
0.22
0.25
0.98
1.11
3.27
3.72
6.54
7.44
3.08
3.51
0
0
0.95
1.08
3.85
4.39
7.7
8.78
1.08
1.23
2.02
2.3
4.62
5.26
2.24
2.55
5.31
6.05
2.49
2.83
3.36
3.82
'Std' Speed
Min. Max.
3.17
0.3
1.31
4.37
8.74
4.13
0
1.27
5.16
10.32
1.45
2.7
6.19
3
7.11
3.33
4.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
v2.7
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