AX1000-1FGG896I Datasheet, PDF (221/226 Pages) Actel Corporation – Axcelerator Family FPGAs

Datasheet Information
Axcelerator Family FPGAs
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v2.7)
v2.6
RoHS-compliant information was added to the "Ordering Information".
ACTgen was changed to SmartGen because ACTgen was obsolete.
v2.5
In Table 2-4, the units for the P_LOAD, P₁₀, and P_I/O were updated from mW/MHz to mW/MHz.
In the "Pin Descriptions"section, the HCLK and CLK descriptions were updated to include tie-off
information.
The "Global Resource Distribution" section was updated.
The " 624-Pin CCGA" table was updated.
v2.4
A note was added to Table 2-2.
In the "Package Thermal Characteristics", the temperature was changed from 150°C to 125°C.
v2.3
Revised ordering information and timing data to reflect phase out of –3 speed grade options.
Table 2-3 was updated.
v2.2
The "Packaging Data" section is new.
Table 2-2 was updated.
"VCCDA Supply Voltage" was updated.
"PRA/B/C/D Probe A/B/C/D" was updated.
The "User I/Os" was updated.
v2.1
Figure 1-3 was updated.
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Table 2-2 was updated.
The "Power-Up/Down Sequence" section was updated.
Table 2-4 was updated.
Table 2-5 was updated.
The "Timing Characteristics" section was added.
Table 2-7 was updated.
Figure 2-1 was updated.
The External Setup and Clock-to-Out (Pad-to-Pad) equations in the "Hardwired Clock – Using
LVTTL 24mA High Slew Clock I/O" section were updated.
The External Setup and Clock-to-Out (Pad-to-Pad) in the "Routed Clock – Using LVTTL 24mA
High Slew Clock I/O" section were updated.
The "Global Pins" section was updated.
The "User I/Os" section was updated.
Table 2-17 was updated.
Figure 2-8 was updated.
Figure 2-13 and Figure 2-14 were updated.
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v2.7
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