AX1000-1FGG896I Datasheet, PDF (64/226 Pages) Actel Corporation – Axcelerator Family FPGAs

Axcelerator Family FPGAs
Routing Specifications
Routing Resources
The routing structure found in Axcelerator devices
enables any logic module to be connected to any other
logic module while retaining high performance. There
are multiple paths and routing resources that can be
used to route one logic module to another, both within a
SuperCluster and elsewhere on the chip.
There are four primary types of routing within the AX
architecture: DirectConnect, CarryConnect, FastConnect,
and Vertical and Horizontal Routing.
DirectConnect
DirectConnects provide a high-speed connection
between an R-cell and its adjacent C-cell (Figure 2-35).
This connection can be made from DCOUT of the C-cell
to DCIN of the R-cell by configuring of the S1 line of the
R-cell. This provides a connection that does not require
an antifuse and has a delay of less than 0.1 ns.
Figure 2-35 • DirectConnect and CarryConnect
CarryConnect
CarryConnects are used to build carry chains for
arithmetic functions (Figure 2-35). The FCO output of the
right C-cell of a two-C-cell Cluster drives the FCI input of
the left C-cell in the two-C-cell Cluster immediately
below it. This pattern continues down both sides of each
SuperCluster column.
Similar to the DirectConnects, CarryConnects can be built
without an antifuse connection. This connection has a
delay of less than 0.1 ns from the FCO of one two-C-cell
cluster to the FCI of the two-C-cell cluster immediately
below it (see the "Carry-Chain Logic" on page 2-45 for
more information).
FastConnect
For high-speed routing of logic signals, FastConnects can
be used to build a short distance connection using a
single antifuse (Figure 2-36 on page 2-51). FastConnects
provide a maximum delay of 0.3 ns. The outputs of each
logic module connect directly to the Output Tracks
within a SuperCluster. Signals on the Output Tracks can
then be routed through a single antifuse connection to
drive the inputs of logic modules either within one
SuperCluster or in the SuperCluster immediately below
it.
Vertical and Horizontal Routing
Vertical and Horizontal Tracks provide both local and
long distance routing (Figure 2-37 on page 2-51). These
tracks are composed of both short-distance, segmented
routing and across-chip routing tracks (segmented at
core tile boundaries). The short-distance, segmented
routing resources can be concatenated through antifuse
connections to build longer routing tracks.
These short-distance routing tracks can be used within
and between SuperClusters or between modules of non-
adjacent SuperClusters. They can be connected to the
Output Tracks and to any logic module input (R-cell,
C-cell, Buffer, and TX module).
The across-chip horizontal and vertical routing provides
long-distance routing resources. These resources
interface with the rest of the routing structures through
2-50
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