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| AX1000-1FGG896I Datasheet, PDF (32/226 Pages) Actel Corporation – Axcelerator Family FPGAs | |||
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Axcelerator Family FPGAs
User I/O Naming Conventions
Due to the complex and flexible nature of the Axcelerator familyâs user I/Os, a naming scheme is used to show the
details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for
differential I/Os (Figure 2-7).
GND
VCCDA
Corner1
VCCI 7
GND
VCCA
GND
VCCDA
GND
VCCI 6
GND
VCCA
GND
GND
V CCDA
Corner4
I/O BANK 0
I/O BANK 1
AX125
I/O BANK 5
I/O BANK 4
Corner2
GND
VCCDA
VCCI 2
GND
VCCA
GND
GND
VCCDA
VCCI 3
GND
VCCA
GND
Corner3
GND
VCCDA
Figure 2-7 ⢠I/O Bank and Dedicated Pin Layout
IOxxXBxFx
Pair number in the
bank, starting at 00,
clockwise from IOB NW
P - Positive Pin/ N- Negative Pin
Bank I/D 0 through 7,
clockwise from IOB NW
Fx refers to an
unimplemented feature
and can be ignored.
Figure 2-8 ⢠General Naming Schemes
Examples:
IO12PB1F1 is the positive pin of the thirteenth pair of the
first I/O bank (IOB NE). IO12PB1 combined
with IO12NB1 form a differential pair.
For those I/Os that can be employed
either as a user I/O or as a special
function, the following nomenclature
is used:
IOxxXBxFx/special_function_name
IOxxPB1Fx/xCLKx this pin can be configured as a clock
input or as a user I/O.
2-18
v2.7
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