A3P1000-1FGG144M Datasheet, PDF (35/181 Pages) Actel Corporation – Military ProASIC3/EL Low-Power Flash FPGAs

Military ProASIC3/EL Low-Power Flash FPGAs
t_EOUT
DQ
E
CLK
t_ZL, t_ZH, t_HZ, t_LZ, t_ZLS, t_ZHS
DQ
D
CLK
EOUT
DOUT
PAD
I/O Interface
D
E
EOUT
PAD
50%
t_{EOUT (R)}
50%
t_ZL
V_{trip VOL}
t_EOUT = MAX(t_EOUT(r), t_EOUT(f))
V_CC
50%
t_{EOUT (F)}
50%
t_HZ
90% V_CCI
V_CC
50%
t_ZH
V_CC
V_CCI
V_trip
50%
t_LZ
10% V_CCI
V_CC
D
E ^50%
EOUT
PAD
t_{EOUT (R)}
50%
V_CC
50%
t_ZLS
V_{trip VOL}
t_{EOUT (F)}
50%
V_OH
V_CC
50%
t_ZHS
V_trip
Figure 2-7 • Tristate Output Buffer Timing Model and Delays (example)
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