A3P1000-1FGG144M Datasheet, PDF (30/181 Pages) Actel Corporation – Military ProASIC3/EL Low-Power Flash FPGAs

Military ProASIC3/EL Low-Power Flash FPGAs
Combinatorial Cells Contribution—P_C-CELL
α P_C-CELL = N_C-CELL* ₁ / 2 * P_AC7 * F_CLK
N_C-CELL is the number of VersaTiles used as combinatorial modules in the design.
α₁ is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on
page 2-19.
F_CLK is the global clock signal frequency.
Routing Net Contribution—P_NET
P_NET = (N_S-CELL + N_C-CELL) * α₁ / 2 * P_AC8 * F_CLK
N_S-CELL is the number of VersaTiles used as sequential modules in the design.
N_C-CELL is the number of VersaTiles used as combinatorial modules in the design.
α₁ is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-21 on
page 2-19.
F_CLK is the global clock signal frequency.
I/O Input Buffer Contribution—P_INPUTS
α P_INPUTS = N_INPUTS * ₂ / 2 * P_AC9 * F_CLK
N_INPUTS is the number of I/O input buffers used in the design.
α₂ is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-19.
F_CLK is the global clock signal frequency.
I/O Output Buffer Contribution—P_OUTPUTS
P_OUTPUTS = N_OUTPUTS * α₂ / 2 * β₁ * P_AC10 * F_CLK
N_OUTPUTS is the number of I/O output buffers used in the design.
α₂ is the I/O buffer toggle rate—guidelines are provided in Table 2-21 on page 2-19.
β₁ is the I/O buffer enable rate—guidelines are provided in Table 2-22 on page 2-19.
F_CLK is the global clock signal frequency.
RAM Contribution—P_MEMORY
β β P_MEMORY = P_AC11 * N_BLOCKS * F_READ-CLOCK * ₂ + P_AC12 * N_BLOCK * F_WRITE-CLOCK * ₃
N_BLOCKS is the number of RAM blocks used in the design.
F_READ-CLOCK is the memory read clock frequency.
β₂ is the RAM enable rate for read operations.
F_WRITE-CLOCK is the memory write clock frequency.
β₃ is the RAM enable rate for write operations—guidelines are provided in Table 2-22
on page 2-19.
PLL Contribution—P_PLL
P_PLL = P_DC4 + P_AC13 *F_CLKOUT
F_CLKOUT is the output clock frequency.¹
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its
corresponding contribution (P_AC13* F_CLKOUT product) to the total PLL contribution.
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