ACE25AC400GL Datasheet, PDF (8/23 Pages) ACE Technology Co., LTD. – SPI NOR FLASH

ACE25AC400GL
SPI NOR FLASH
Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may
be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one
of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending
a new command to the device. It is also possible to read the Status Register continuously.
Figure3. Read Status Register Sequence Diagram
Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After
the Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable
Latch (WEL).
The Write Status Register (WRSR) command has no effect on S6, S5, S1 and S0 of the Status Register.
CS# must be driven high after the eighth bit of the data byte has been latched in. If not, the W rite Status
Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the
Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect
(BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1.1 and 1.2. The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP)
bit, the Write Status Register (WRSR) command allows the user to set the Status Register Write Disable
(SRWD) bit to 1. The Status Register Write Disable (SRWD) bit allow the device to be put in another
Software Protected Mode. Once the SRWD bit is set to 1, the Write Status Register (WRSR) command is
not executed, and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
Figure4. Write Status Register Sequence Diagram
VER 1.1 8