ACE25AC400GL Datasheet, PDF (4/23 Pages) ACE Technology Co., LTD. – SPI NOR FLASH

ACE25AC400GL
SPI NOR FLASH
Device Operation
The ACE25AC400GL features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of
SCLK.
Data Protection
The ACE25AC400GL provides the following data protection methods:
Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
 Power-Up
 Write Disable (WRDI)
 Write Status Register (WRSR)
 Page Program (PP)
 Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
Software Protection Mode:
 SRWD=0, the Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be
read but not change
 SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the
SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
Table 1.ACE25AC400GL Protected Area Sizes
Status bit
BP2
BP1
BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protect level
0(none)
1 (1 block)
2 (2 blocks)
3 (4 blocks)
4 (8 blocks)
5 (All)
6 (All)
7 (All)
Protect Block
None
Block 7
Block 6-7
Block 4-7
All
All
All
All
VER 1.1 4