ACE25C512 Datasheet, PDF (7/34 Pages) ACE Technology Co., LTD. – 512K-BIT Serial Flash Memory

ACE25C512
512K-BIT Serial Flash Memory
level at power-up until the VCC-min level and t_VSL time delay is reached. If needed a pull-up resister
on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register
Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page
Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted.
After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically
cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the W rite Status Register instruction and
setting the Status Register Protect (SRP) and Block Protect (BP2, BP1 and BP0) bits. These settings
allow a portion as small as a 4KB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be enabled
or disabled under hardware control. See Status Register section for further information. Additionally,
the Power-down instruction offers an extra level of write protection as all instructions are ignored
except for the Release Power-down instruction.
Status Register
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, the state of write protection, Security Sector
lock status. The Write Status Register instruction can be used to configure the device write protection
features and Security Sector OTP lock. Write access to the Status Register is controlled by the state
of the non-volatile Status Register Protect bit (SRP), the Write Enable instruction, and the WP# pin.
Factory default for all Status Register bits are 0.
Figure 4 Status Register
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