ACE25C512 Datasheet, PDF (6/34 Pages) ACE Technology Co., LTD. – 512K-BIT Serial Flash Memory

ACE25C512
512K-BIT Serial Flash Memory
the DI and DO pins become bidirectional I/O pins: DQ₀ and DQ₁.
Hold
For Standard SPI and Dual SPI operations, the HOLD# signal allows the ACE25C512 operation to
be paused while it is actively selected (when CS# is low). The HOLD# function may be useful in cases
where the SPI data and clock signals are shared with other devices. For example, consider if the page
buffer was only partially written when a priority interrupt requires use of the SPI bus. In this case the
HOLD# function can save the state of the instruction and the data in the buffer so programming can
resume where it left off once the bus is available again.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will
activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not
already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD# condition
will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If the CLK is not
already low the HOLD# condition will terminate after the next falling edge of CLK. During a HOLD#
condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock
(CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) for the full duration of the
HOLD# operation to avoid resetting the internal logic state of the device.
Figure 3 Hold condition waveform
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and
other adverse system conditions that may compromise data integrity. To address this concern, the
ACE25C512 provides several means to protect the data from inadvertent writes.
Write Protect Features
 Device resets when VCC is below threshold
 Time delay write disable after Power-up
 Write enable/disable instructions and automatic write disable after erase or program
 Software and Hardware (WP# pin) write protection using Status Register
 Write Protection using Power-down instruction
 Lock Down write protection for Status Register until the next power-up
 One Time Program (OTP) write protection for array and Security Sectors using Status Register.
Upon power-up or at power-down, the ACE25C512 will maintain a reset condition while VCC is
below the threshold value of VWI, (See “12.3 Power-up Timing” and Figure 23). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC
voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay
of t_PUW. This includes the Write Enable, Page Program, Sector Erase, Block Er ase, Chip Erase and
the Write Status Register instructions. Note that the chip select pin (CS#) must track the VCC supply
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