ACE25C512 Datasheet, PDF (10/34 Pages) ACE Technology Co., LTD. – 512K-BIT Serial Flash Memory

ACE25C512
512K-BIT Serial Flash Memory
Block erase (32KB) 52h
A23-A16
A15-A8 A7-A0
Block erase (64KB) D8h
A23-A16
A15-A8 A7-A0
Chip erase
C7h/60h
Power-down
B9h
Read data
03h
A23-A16
A15-A8 A7-A0
D7-D0
Fast read
0Bh
A23-A16
A15-A8 A7-A0 dummy
D7-D0
Release
powerdown/ID ⁽⁴⁾
ABh
Read Unique ID⁾
4Bh
dummy
dummy
dummy
dummy
dummy (ID7-D0)⁽²⁾
dummy dummy (UID63-UID0)
Manufacturer/Device
ID ⁽⁴⁾
90h
dummy
dummy
00h (MF7-MF0) (ID7-D0)
JEDEC ID ⁽⁴⁾
(ID15-ID8)
9Fh
(MF7-MF0) _Memory (ID7-D0)
Manufacturer _Type Capacity
Enter OTP mode
3Ah
Table 4 Standard SPI Instruction Set ⁽¹⁾
Dual SPI instructions Set
Instruction Name Byte 1 Byte 2
Byte 3
Byte 4 Byte 5 Byte 6
Clock number
Fast read dual output
Fast read dual I/O
(0-7)
3Bh
BBh
(8-15)
A23-A16
A23-A8 ⁽⁵⁾
(16-23)
A15-A8
A7-A0, M7-M0 ⁽⁵⁾
(24-31)
A7-A0
(D7-DO,…)⁽⁶⁾
(32-39)
dummy
(40-47)
(D7-D0,…)⁽⁶⁾
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the
device on 1 or 2 DQ pins.
2. The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction.
3. At least one byte of data input is required for Page Program and Program Security Sectors, up to 256 bytes of data input. If
more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite
previously sent data.
4. See Table 3 Manufacturer and Device Identification table for device ID information.
5. Dual SPI address input format:
DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
6. Dual SPI data output format: DQ0 = (D6, D4, D2, D0) DQ1 = (D7, D5, D3, D1)
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status
Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase,
Chip Erase, Write Status Register instruction. The Write Enable (WREN) instruction is entered by
driving CS# low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of
CLK, and then driving CS# high.
VER 1.2 10