ACE25C512 Datasheet, PDF (19/34 Pages) ACE Technology Co., LTD. – 512K-BIT Serial Flash Memory

ACE25C512
512K-BIT Serial Flash Memory
Figure 16 32KB Block Erase Instruction (SPI Mode)
64KB Block Erase (BE) (D8h)
The 64KB Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased
state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the
Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving
the CS# pin low and shifting the instruction code “D8h” followed a 24-bit block address A23-A0. The
Block Erase instruction sequence is shown in Figure 17.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not
done the Block Erase instruction will not be executed. After CS# is driven high, the self -timed Block
Erase instruction will commence for a time duration of t_BE (See 12.6 AC Electrical Characteristics”).
While the Block Erase cycle is in progress, the Read Status Register instruction may still be accessed
for checking the status of the WIP bit. The WIP bit is a 1 during the Block Erase cycle and becomes a
0 when the cycle is finished and the device is ready to accept other instructions again. After the Block
Erase cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Block Erase instruction will not be executed if the addressed page is protected by the Block Protect
(BP2, BP1, and BP0) bits (see Table 2 Status Register Memory Protect ion table).
Figure 17 Block erase instruction
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