ACE25Q200G Datasheet, PDF (38/46 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH Memory Series

ACE25Q200G
2M BIT SPI NOR FLASH Memory Series
Erase / Program Resume (7AH)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block
Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume
instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to
1 and the WIP bit equals to 0.
After the Resume instruction is issued the SUS bit will be cleared from 1 to 0 immediately, the WIP
bit will be set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation or
the page will complete the program operation. If the SUS bit equals to 0 or the WIP bit equals to 1,
the Resume instruction “7Ah” will be ignored by the device. The Erase/Program Resume
instruction sequence is shown in Figure 31.
Figure 31 Erase/Program Resume Command Sequence
Figure 31
Reset Device Instructions
Enable Reset (7Eh) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the ACE25Q200G provides
a software Reset instruction instead of a dedicated RESET pin. Once the software Reset
instruction is accepted, any on-going internal operations will be terminated and the device will
return to its default power-on state and lose all the current volatile settings, such as Volatile Status
Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Continuous Read
Mode bit setting (M7-M0) and Wrap Bit setting (W6-W4).
To avoid accidental reset, both “Enable Reset (7Eh)” and “Reset (99h)” instructions must be
issued in sequence. Any other commands other than “Reset (99h)” after the “Enable Reset (7Eh)”
command will disable the “Reset Enable” state. A new sequence of “Enable Reset (7Eh)” and
“Reset (99h)” is needed to reset the device. Once the Reset command is accepted by the device,
the device will take approximately 30us to reset. During this period, no command will be accepted.
The Enable Reset (7Eh) and Reset (99h) instruction sequence is shown in Figure 32.
Data corruption may happen if there is an on-going or suspended internal Erase or Program
operation when Reset command sequence is accepted by the device. It is recommended to check
the BUSY bit and the SUS bit in Status Register before issuing the Reset command sequence.
Figure 32 Reset (7Eh) and Reset (99h) Command Sequence
Figure 32
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