ACE25Q200G Datasheet, PDF (32/46 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH Memory Series

ACE25Q200G
2M BIT SPI NOR FLASH Memory Series
Program Security Registers (42H)
See Figure 24, the Program Security Registers instruction is similar to the Page Program
instruction. It allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit before sending the
Program Security Registers instruction. The Program Security Registers instruction is entered by
driving /CS Low, followed by the instruction code (42H), three address bytes and at least one data
byte on SI. As soon as /CS is driven high, the self-timed Program Security Registers cycle (whose
duration is tPP) is initiated. While the Program Security Registers cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Program Security Registers cycle, and is
0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable
Latch bit is reset.
If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be
permanently locked. Program Security Registers instruction will be ignored.
Table 12
Address
A23-A16
A15-A8
A7-A0
Security Registers 1
00H
01H
Byte Address
Security Registers 2
00H
02H
Byte Address
Security Registers 3
00H
03H
Figure 24 Program Security Registers instruction Sequence Diagram
Byte Address
Figure 24
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