ACE25Q200G Datasheet, PDF (34/46 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH Memory Series

ACE25Q200G
2M BIT SPI NOR FLASH Memory Series
Sector Erase (20H)
The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by
driving /CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is a
valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the sequence.
See Figure 26, the Sector Erase instruction sequence: /CS goes low sending Sector Erase instruction
3-byte address on SI /CS goes high. The instruction sequence is shown in Figure18. /CS must be driven high
after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase instruction is not
executed. As soon as /CS is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated.
While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when
it is completed.
At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset. A Sector Erase instruction applied to a sector which is protected by the Block Protect (SEC, TB, BP2,
BP1, BP0) bits (see Table 6 & 7) is not executed.
Figure 26 Sector Erase Sequence Diagram
Figure 26
VER 1.2 34