ACE25Q200G Datasheet, PDF (36/46 Pages) ACE Technology Co., LTD. – 2M BIT SPI NOR FLASH Memory Series

ACE25Q200G
2M BIT SPI NOR FLASH Memory Series
64KB Block Erase (D8H)
The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit. The 64KB Block
Erase instruction is entered by driving /CS low, followed by the instruction code, and three address
bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase instruction.
/CS must be driven low for the entire duration of the sequence.
See Figure 28, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB Block
Erase instruction 3-byte address on SI /CS goes high. The instruction sequence is shown in Figure20.
/CS must be driven high after the eighth bit of the last address byte has been latched in; otherwise the
64KB Block Erase instruction is not executed. As soon as /CS is driven high, theself-timed Block
Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 64KB Block
Erase instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0)
bits (see Table 6 & 7) is not executed.
Figure 28 64KB Block Erase Sequence Diagram
Figure 28
VER 1.2 36