IS66WV51216ALL Datasheet, PDF (10/16 Pages) Integrated Silicon Solution, Inc – 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM

IS66WV51216ALL
IS66WV51216BLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
55 ns
70 ns
Symbol Parameter
Min. Max.
Min. Max.
Unit
twc
Write Cycle Time

55
—
70 —
ns
tscs1/tscs2 CS1/CS2 to Write End

45
—
60 —
ns
taw
Address Setup Time to Write End
45
—
60 —
ns
tha
Address Hold from Write End

0
—
0 —
ns
tsa
Address Setup Time

0
—
0 —
ns
tpwb
LB, UB Valid to End of Write

45
—
60 —
ns
tpwe⁽⁴⁾
WE Pulse Width

45
—
60 —
ns
tsd
Data Setup to Write End

25
—
30 —
ns
thd
Data Hold from Write End

0
—
0 —
­ns
thzwe⁽³⁾ WE LOW to High-Z Output

—
20
— 30
ns
tlzwe⁽³⁾ WE HIGH to Low-Z Output

5
—
5 —
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of0.4 to
Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.
4. tpwe > thzwe + tsd when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1^(1,2) (CS1 Controlled, OE = HIGH or LOW)
ADDRESS
CS1
CS2
WE
LB, UB
DOUT
DIN
tWC
tSCS1
tHA
tSCS2
tAW
tPWE
tPWB
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
12/02/09