S1M8660A Datasheet, PDF (14/32 Pages) Samsung semiconductor – RX IF / BBA WITH GPS

S1M8660A (Preliminary)
RX IF/BBA WITH GPS
Ultimately, I and Q filtered signals are converted to digital signals by the 4-bit A-D converter and sent to the
modem. The A-D converter used is a parallel output type and its outputs are synchronized at the CHIPx8 rising
edge. The modem chip captures the data on the CHIPx8 falling edge. The CHIPx8 clock used in the A-D
converter can change the CHIP×8 output to input so that the clock can be used in systems with different TCXO
reference frequency.
FM Rx Signal Path
S1M8660A FM signal path is the same as that of the CDMA with the exception of a different LPF and A-D
converter, which meet the system specification. Basically a FM modulated signal between IF mid-frequency to
±15kHz is input so that the baseband LPF, unlike CDMA, has the 12kHz cut-off frequency characteristic. A-D
Converter has 8-bit resolution, characteristic of AMPS, and processing speed of approx. 40kHz. It does not adopt
the power consuming parallel configuration but rather the series configuration to minimize the consumption
power.
Rx AGC , connected to both the IF SAW filter and matching component in the RF-IF converter output located in
the RF block, amplifies or reduces according to the signal size. It takes its orders from the modem chip when it
sets the appropriate receive level as required by the CDMA system. Gain is controlled by applying a DC voltage
to the RAGC_CONT pin. The applied DC is produced when the PDM signal, generated as a control signal in the
modem, passes through the R-C filter. The control band of this AGC is approx. 90dB. The QPSK Baseband
modulator separates and modulates the IF signal sent by the AGC using I(In-phase) and Q(Quad-phase)
baseband signals. Essentially, two signals, I-LO and Q-LO (Local oscillator), are mixed with AGC's IF output
signals, respectively. The LO(local oscillator) signal is generated by the internal oscillating component, externally
connected tank coil, and Varactor, and the externally independent PLL device is used to generate its exact
oscillation mid-frequency. Defining of the I-Phase and Q-Phase receive path is very important to its design. The
polarities of these paths are also important to digital baseband modulation. Therefore, the output of the QPSK
baseband modulation determines the I and Q phases; I-phase is defined as the phase leading the Q-phase by
exactly 90°, but it simpler to think of I as Cosin and Q as Sin.
T=0
Q-CH
I-CH
Figure 6. Received I/Q Phase in S1M8660A
The figure related to this is shown in Figure 6. This definition is valid only when the QPSK IF input signal is
higher than the IF mid-frequency. The baseband signal, output by the QPSK modulator, includes various other
unnecessary surrounding band noises, which are removed by the use of the LPF(Low-Pass-Filter). The filter pole
is barely 12kHz , merely in the audible range, for AMPS considering that the CDMA is 630kHz. Ultimately, I and
Q filtered signals are converted to digital signals by the 4-bit A-D converter and sent to the modem. The A-D
converter used is a parallel output type ;its outputs are synchronized at the FMCLK and output in the order that it
was synchronized. The modem chip captures the data by matching the FMDATA to the FMCLK clock. The
CHIPx8 clock used in the A-D converter can change the CHIP×8 output to input so that the clock can be used in
systems with different TCXO reference frequency. The clock used by the A-D converter is provided by the
modem chip. It has a 360kHz frequency but can have 40kHz cycle when converting an 8-bit data.
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