X9118_14 Datasheet, PDF (5/17 Pages) Intersil Corporation – Single Digitally-Controlled Potentiometer

X9118
SCL FROM
MASTER
1
DATA OUTPUT
FROM TRANSMITTER
8
9
DATA OUTPUT
FROM RECEIVER
START
FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACKNOWLEDGE
ACKNOWLEDGE POLLING
The disabling of the inputs during the internal nonvolatile write
operation, can be used to take advantage of the typical 5ms
EEPROM write cycle time. Once the stop condition is issued to
indicate the end of the nonvolatile write command the X9118
initiates the internal write cycle. The ACK polling, Flow 1, can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9118 is
still busy with the write operation no ACK will be returned. If the
X9118 has completed the write operation an ACK will be
returned and the master can then proceed with the next
operation.
Flow 1. ACK Polling Sequence
NONVOLATILE WRITE
COMMAND COMPLETED
ENTERACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
NO
RETURNED?
YES
INSTRUCTION AND REGISTER DESCRIPTION
Device Addressing: Identification Byte (ID and A)
Following a start condition, the master must output the
address of the slave it is accessing. The most significant
4 bits of the slave address are the device type identifier. The
ID[3:0] bits is the device ID for the X9118; this is fixed as
0101[B] (refer to Table 1 on page 6).
The A[1:0] bits in the ID byte are the internal slave address.
The physical device address is defined by the state of the
A1-A0 input pins. The slave address is externally specified
by the user. The X9118 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9118 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A1 to A0 inputs can
be actively driven by CMOS input signals or tied to V_CC or
V_SS. The R/W bit is the LSB and used to set the device for
read or write operations.
INSTRUCTION BYTE AND REGISTER SELECTION
The next byte sent to the X9118 contains the instruction and
register pointer information. The three most significant bits
are used to provide the instruction opcode (I[2:0]). The RB
and RA bits point to one of the four registers. The format is
shown in Table 2.
Table 3 provides a complete summary of the instruction set
opcodes.
FURTHER
NO
OPERATION?
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
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5
FN8161.5
April 9, 2014