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U6264AS1A07 Datasheet, PDF (4/8 Pages) Zentrum Mikroelektronik Dresden AG – Automotive 8K x 8 SRAM
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U6264ASA07
Switching Characteristics
Time to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address
Change
E1 HIGH or E2 LOW to Output in
High-Z
W LO W to Output in High-Z
G HIGH to Output in High-Z
Symbol
Alt.
IEC
tLZ
tt(QX)
Min. Max.
5
10
tWC
tcW
70
-
tRC
tcR
70
-
tACE
ta(E)
-
70
tOE
ta(G)
-
40
tAA
ta(A)
-
70
tWP
tw(W)
50
-
tCW
tw(E)
65
-
tAS
tsu(A)
0
-
tCW
tsu(E)
65
-
tWP
tsu(W)
50
-
tDS
tsu(D)
35
-
tDH
th(D)
0
-
tAH
th(A)
0
-
tOH
tv(A)
5
-
tHZCE
tdis(E)
0
25
tHZWE
tdis(W)
0
30
tHZOE
tdis(G)
0
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
4.5 V
VCC
4.5 V
VCC
VCC(DR) ≥ 2 V
VCC(DR) ≥ 2 V
E2
2.2 V
2.2 V
tDR
Data Retention
trec
E1
tDR
Data Retention
trec
0.8 V
VE2(DR) ≤ 0.2 V
0.8 V
0V
0V
VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
tDR: min 0 ns
trec: min tcR
4
December 12, 1997
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