U635H256 Datasheet, PDF (12/13 Pages) Simtek Corporation – PowerStore 32K x 8 nvSRAM

U635H256
SOFTWARE NONVOLATILE RECALL
A RECALL cycle of the EEPROM data into the SRAM
is initiated with a sequence of READ operations in a
manner similar to the STORE initiation. To initiate the
RECALL cycle the following sequence of READ opera-
tions must be performed:
1. Read addresses 0E38 (hex) Valid READ
2. Read addresses 31C7 (hex) Valid READ
3. Read addresses 03E0 (hex) Valid READ
4. Read addresses 3C1F (hex) Valid READ
5. Read addresses 303F (hex) Valid READ
6. Read addresses 0C63 (hex) Initiate RECALL
Cycle
Internally, RECALL is a two step procedure. First, the
SRAM data is cleared and second, the nonvolatile
information is transferred into the SRAM cells. After
t_d(E)R cycle time the SRAM will once again be ready for
READ and WRITE operations.The RECALL operation
in no way alters the data in the EEPROM cells. The
nonvolatile data can be recalled an unlimited number of
times.
HARDWARE PROTECTION
The U635H256 offers hardware protection against
inadvertent STORE operation through V_CC Sense.
When V_CC < V_SWITCH all software STORE operations
will be inhibited.
LOW AVERAGE ACTIVE POWER
The U635H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the V_CC level
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December 12, 1997