Z80230 Datasheet, PDF (8/12 Pages) Zilog, Inc. – ESCC™ ENHANCED SERIAL COMMUNICATION CONTROLLER

AC CHARACTERISTICS
Z80230 Read/Write Timing Table (Continued)
No Symbol
Parameter
10 MHz
Min Max
16 MHz
Min Max
Notes*
41 TwPCh
42 TcPC
43 TrPC
44 TfPC
PCLK High Width
PCLK Cycle Time
PCLK Rise Time
PCLK Fall Time
40 1000
100 2000
10
10
26 1000
61 2000
5
5
Notes:
[1] Parameter does not apply to Interrupt Acknowledge transactions.
[2] Parameter applies only between transactions involving the SCC.
[3] Float delay is defined as the time required for a ± 0.5V change in the output with a maximum DC load and a minimum AC load.
[4] Open-drain output, measured with open-drain test load.
[5] Parameter is system dependent. For any Z-SCC in the daisy chain. TdAS(DSA) must be greater than the sum of TdAS(IEO) for the highest priority
device in the daisy chain. TslEl(DSA) for the Z-SCC, and TdlElf(IEO) for each device separating them in the daisy chain.
[6] Parameter applies only to a Z-SCC pulling INT Low at the beginning of the Interrupt Acknowledge transaction.
[7] Internal circuitry allows for the reset provided by the Z8 to be recognized as a reset by the Z-SCC. All timing references assume 2.0V for a logic
"1" and 0.8V for a logic "0".
* Units in nanoseconds (ns).
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