Z80230 Datasheet, PDF (10/12 Pages) Zilog, Inc. – ESCC™ ENHANCED SERIAL COMMUNICATION CONTROLLER

AC CHARACTERISTICS
Z80230 General Timing Table
No Symbol
Parameter
10 MHz
Min Max
16 MHz
Min Max
Notes*
1 TdPC(REQ)
/PCLK Low to W/REQ Valid
2 TsPC(W)
/PCLK Low to Wait Inactive
3 TsRXC(PC)
/RxC High to /PCLK High Setup Time
4 TsRXD(RXCr) RxD to /RxC High Setup Time
200
300
NA
0
110
180
NA
0
[1,4]
[1]
5 ThRXD(RxCr) RxD to /RxC High Hold Time
6 TsRXD(RXCf) RxD to /RxC Low Setup Time
7 ThRXD(RXCf) RxD to /RxC Low Hold Time
8 TsSY(RXC)
SYNC to /RxC High Setup Time
125
0
125
-150
60
0
60
-100
[1]
[1,5]
[1,5]
[1]
9 ThSY(RXC)
10 TsTXC(PC)
11 TdTXCf(TXD)
12 TdTxCr(TXD)
SYNC to /RxC High Hold Time
/TxC Low to /PCLK High Setup Time
/TxC Low to TxD Delay
/TxC High to TxD Delay
5TcPc
NA
150
150
5TcPc
NA
85
85
[1]
[2,4]
[2]
[2,5]
13 TdTXD(TRX)
14 TwRTXh
15 TwRTXl
16a TcRTX
TxD to TRxC Delay
RTxC High Width
TRxC Low Width
RTxC Cycle Time
140
120
120
400
80
80
80
244
[6]
[6]
[6,7]
16b TxRX(DPLL)
17 TcRTXX
18 TwTRXh
19 TwTRXl
DPLL Cycle Time Min
Crystal Osc. Period
TRxC High Width
TRxC Low Width
50
100 1000
120
120
31
100 1000
80
80
[7,8]
[3]
[6]
[6]
20 TcTRX
21 TwEXT
22 TwSY
TRxC Cycle Time
DCD or CTS Pulse Width
SYNC Pulse Width
400
244
[6,7]
120
70
120
70
Notes:
[1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3] Both /RTxC and /SYNC have 30 pf capacitors to ground connected to them.
[4] Synchronization of RxC to PCLK is eliminated in divide by four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to case PCLK requirements.
[7] The maximum receive or transmit data rate is 1/4 PCLK.
[8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK still applies. DPLL clock should have a 50% duty cycle.
* Units in nanoseconds (ns).
10