Z8F2480 Datasheet, PDF (6/24 Pages) Zilog, Inc. – Load current up to 3 amps

Z8F2480 Power Monitor with an eZ80F91 Webserver
Reference Design
The final step performed during system initialization is to configure the Z8F2480 MCU’s
Multi-Channel Timer (MCT) to capture time stamps (measured in IPO clock ticks) just
before, and just after, the full-wave rectified (FWR) amplifier output signal goes through a
zero crossing (using the voltage on R26 as a reference threshold). These time stamps are
captured by connecting the amplifier output to the noninverting input of the Z8F2480
MCU’s Internal Comparator C0 and connecting the threshold voltage to the inverting
input of Comparator C0. The output of Comparator C0 is connected to MCT channels C
and D, and the MCT is configured such that a time stamp is captured on the rising edge
(Channel C) and falling edge (Channel D) of C0OUT. MCT channels A and B are simi-
larly configured to capture time stamps on the rising and falling edges of the output of
Comparator C1, which is High for most of the positive AC half-cycle when the voltage on
R9 exceeds the Z8F2480 MCU’s internal reference voltage of 0.4 V.
MCT interrupts are used to measure the AC period and estimate when the next amplifier
output peak will occur. This estimate of when the next peak occurs will only be accurate if
the load signal is periodic and if the actual AC peak occurs at the exact midpoint between
the rising and falling edges of the output of Comparator C0 (e.g., the load signal is sinusoi-
dal). If the load signal meets these conditions, then a secondary timer can be used to gen-
erate an interrupt just before the next expected amplifier output peak, thereby allowing the
software to obtain ADC samples to measure the peak AC voltage/load current.
The Z8F2480 firmware maintains a rolling average of the number of IPO clock ticks
between the last nine HWR peak AC voltages on R9. An instantaneous period is calcu-
lated by subtracting the time stamp of the last HWR AC peak voltage (i.e., the midpoint of
the Channel A and Channel B time stamps) from the time stamp of the current HWR AC
peak voltage. The average period is recalculated on each MCT Channel B interrupt (C1
falling edge) using the last eight delta-times between HWR peaks.
Because the AC period remains relatively constant between zero crossings of the FWR
amplifier output, software can set a timeout to occur just before a half-period from the
location of the last amplifier output peak (i.e., the midpoint of the MCT Channel C and
Channel D time stamps). When the timer expires, a fixed number of ADC samples are
taken such that the sampling window begins just before the expected peak occurs and ends
just after the expected peak occurs. The largest ADC reading observed during this sam-
pling interval determines the peak voltage of the amplifier output signal.
ADC measurements are taken for both FWR peaks that occur during each AC period. The
FWR amplifier output peak that occurs within a quarter of a period of the HWR voltage
peak is referred to as the positive peak, and the FWR peak that is more than a quarter-
period from the HWR peak is the negative peak. When reporting the AC voltage and load
current to the eZ80F91 webserver, the positive and negative peak values are averaged to
provide the voltage and current amplitudes, thereby eliminating offset errors that might be
introduced by the signal conditioning and amplification circuit.
By periodically toggling Switch U5-A, the software can alternate between measuring the
amplitude of the load current (i.e., the voltage drop across R8) and the amplitude of the
FWR AC voltage (the voltage drop across RS4) through the Z8F2480 MCU’s ADC block.
The software changes the position of Switch U5-A every 9 AC periods just after the fall-
ing edge of the negative FWR half-cycle. No ADC samples are taken during the AC
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