Z8FMC16MCU Datasheet, PDF (14/14 Pages) Zilog, Inc. – Z8 Encore-R Motor Control Series

Z8FMC16 MCU
Programming Specification
12
Z8FMC16100 Flash Programming Flowchart
Figure 8 illustrates an example flowchart for read and write operations.
Z8FMC16100 Flash Programming Flowchart
START
RESET&
DBG Low
Release
RESET
R eleas e
DBG
5 ms
20us
Wait f or
break
Autobaud
W rit eOC D
0x 80
Mass
Erase
Flash?
N
o _WrTestmode
Register
W rit eOC D
0x F 0
XINis
Sy sClk
OSCCT L E2
W rit eOC D
0x 08,
0x 0F ,
0x 86,
0x 01,
0x E2
OSCCT L 18
W rit eOC D
0x 08,
0x 0F ,
0x 86,
0x 01,
0x 18
OSCCT L E7
W rit eOC D
0x 08,
0x 0F ,
0x 86,
0x 01,
0x E7
FFREQH^* 4E
FFREQL^* 20
W rit eOC D
0x 08,
0x 0F ,
0x F A,
0x 01,
0x 4E
W rit eOC D
0x 08,
0x 0F ,
0x F B,
0x 01,
0x 20
Autobaud
W rit eOC D
0x 80
FCT L 73
Unlockstep1
W rit eOC D
0x 08,
0x 0F ,
0x F 8,
0x 01,
0x 73
FCT L 8C
Unlockstep2
W rit eOC D
0x 08,
0x 0F ,
0x F 8,
0x 01,
0x 8C
250 ms
Autobaud
W rit eOC D
0x80
FCT L 63
Iss ues Masserase
W rit eOC D
0x 08,
0x 0F ,
0x F 8,
0x 01,
0x63
W rit eOC D
0x 04
Val ueforWr
T es tmode
Register
Flash
Controller
By passed
SEL =
PW M2H , PW M1L, PW M1H
DIO =
PW M2L, POR T[ A6: A0]
* The Values f or FFREQH and FFREQL are based
on a 20MHz clock source. This v alue is set by the
f ollowing equation
{FFREQH[7:0],FFREQL[7:0]}=(ClockFrequency )/
1000
0x4e20= (20 MHz)/1000
Set
T MR
SEL = 0x04
& DIN =0x 80
TEST
1
Wr/Rd
Memory ?
Re ad
SEL= 0x 03
D I N =0x F 0
Write
Set ADDRH
SEL = 0x00
DIN =addr[15:8]
DeassertYE
SEL=0x03
DIN =0x85
30 us
Do not use less then a 32kHz clock source.
Se tA DDRL
SEL = 0x01
D I N =addr[ 7: 0]
As sertXE&
PROG
SEL = 0x03
DIN =0x84
As sertYE
SEL = 0x03
D I N =0x C 5
SetDAT A
SEL = 0x02
D I N =dat a[ 7: 0]
As sertNVST R
SEL=0x03
DIN =0x85
5 us
SetADDRL
SEL = 0x01
D I N =addr[ 7: 0]
10 us
Wr Done
Yes
20ns
Set ADDRH
SEL = 0x00
DIN =addr[15:8]
SetADDRL
SEL = 0x01
D I N =addr[ 7: 0]
No, increm ent YADDR
Dea s s e rtP ROG
De as s e rtXE &
NVST R
SEL=0x03
SEL=0x03
DIN =0x81
DIN =0x00
5 us
1 us
Address Val idto
DataVal id
SEL = 0x05
D OU T =dat a[ 7: 0]
45 ns
No, increm ent YADDR
Rd Loop
Done
STOP
Yes
Figure 8. Z8FMC16100 Flash Gang Programming Flow
PRS000502-1005
PRELIMINARY
Flash Memory Programming Overview