PDSP16510A Datasheet, PDF (9/23 Pages) Mitel Networks Corporation – Stand Alone FFT Processor

PDSP16510A
input. When DEN and DOS are both active an internal read
operation occurs, and an address generator is incremented.
DAV goes in-active in response to the DOS edge needed to
read the last output, unless Bit 15 in the Control Register is set.
In this case DAV goes in-active when the next INEN edge is
received for reasons given later.
In host controlled systems the time to dump data could be
longer than the transform time. The dump time in such a
system will dictate the maximum sampling rate that can be
used without the loss of incoming data. In the 1024 point
mode, when the loss of data is not important, the PDSP16510
is designed to not accept new data until the previous results
have been dumped. Such a system needs no input buffer, and
INEN can be permanently tied low if the edge activated mode
is not in use. If the loss of data is to be avoided an input buffer
is needed and the host must have received all the results
before a new block of data has been loaded into the buffer.
For 256 point transforms, with host controlled dumping,
it is still possible to overlap load and dump operations. The
maximum dump times, however, must be less than the load
times to avoid data corruption. Previously converted outputs
will be actually corrupted, rather than inputs simply not being
used.
If the loss of incoming data is not important, the device
can be forced to do separate load, transform, and then dump
operations. The corruption of results will then never occur, no
matter what dump time is taken. This can be achieved by
ensuring that INEN is not active between loading a block of
data and completing the dump of the results from that data.
The same ends can be achieved if the INEN edge activated
mode ( Bit 12 reset ) is used, and the inverted DAV edge is
used to drive the INEN input. This then initializes a new load
operation only when the previous dump has been completed.
Results are transferred from the device with the rising
edge of the DOS strobe when DEN is active. This is consistent
with using the device in a data flow architecture, as is com-
monly employed in data processing systems. In a typical
microprocessor based system, however, data is normally
expected to become valid before the end of the data strobe
produced by the processor. It is thus necessary for the user
to provide a ‘dummy’ data strobe in order to transfer data to
the outputs which can then be read by the host during the next
data strobe. In addition further ' dummy ' strobes are needed
each time DAV goes active in order to prime the output
circuitry. The actual output sequence is given in Table 3 for a
single device systemand is described more fully in "user notes
- stopping DOS".
GENERAL DUMP CONSIDERATIONS
The tri-state drivers on the output buses are only enabled
when both DAV and DEN are active. When DEN is tied
permanently low the output bus will start to become valid from
the DOS edge which also generates the DAV output. The next
DOS edge can then be used to transfer the first output to the
next device. When DEN is driven low in response to the DAV
output, the outputs start to become valid when DEN goes low.
The Scale Tag outputs become valid at the same time as data,
and when enabled will continue to indicate the correct value
until all frequency bins have been dumped. If at any time
during the dump operation DEN goes in- active, then both the
DAV
DEN
DOS
Dummy Strobes
(1)
(2)
(3)
TPS
TPW
TPH
(4)
DATA
Un-defined
O/P
TLZ
TDD
O/P 1
THZ
O/P 1
TOH
O/P 2
S3:0
Un-defined
Scale Tag Value
In this zone SCLK and DOS requirements have to be met - See "User Notes - stopping DOS"
Scale Tag Value
Characteristic
Symbol
16510A,A0,B0,C0
Min
Max
TVI
O/P N
THZ
Units
DEN Set Up Time
Host Strobe Width
DEN Hold Time
DAV in-active going Delay ( 30 pf load )
Output Enable Time ( see Fig 13 )
Output Data Delay Time ( 30 pf load )
Output Disable Time ( see Fig 13 )
Read Cycle Time
Old Data Hold Time
T
10
PS
T_PW
10
T_PH
5
T_VI
10
T_LZ
10
T_DD
15
T
10
HZ
T_RC
25
T_OH
2
Table 3. Host Controlled Output Timing. ( Advanced Data )
ns
ns
ns
ns
ns
ns
ns
ns
ns
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