PDSP16510A Datasheet, PDF (13/23 Pages) Mitel Networks Corporation – Stand Alone FFT Processor

PDSP16510A
Data). This bit must not be set in the other devices. Since all
devices are supplied from a common input bus and have a
common source of control parameters, this Bit 12 inversion is
best mechanized with an Exclusive OR gate in the AUX12
input line of the first device. The input can then be inverted
when DEF is active but otherwise not be effected. Once the
first device has been started with the DEF edge, the sequence
will continue automatically using the LFLG /INEN connection
between devices.
In many applications data is transformed continuously
after power on, and the concept of a first data sample does not
exist. If, however , the opposite is true, the first data sample
must be present on the input pins such that it can be loaded
with the second rising DIS edge after DEF has gone in-active.
The data must meet the set up and hold times given in Table
1, and DEF itself must meet the parameters normally met by
the INEN rising edge. The latter requirement is necessary to
avoid a possible one DIS cycle variance, due the internal DEF
synchronization logic. If the position of the first data sample is
not important, it is not necessary for DEF to have any set up
specification.
Without the feedback from the last device, the first device
would wait for another externally supplied initialising pulse. In
such a system with N devices in parallel, then N continuous
transforms must be executed before the first device can wait
for a new INEN input.
When only one output processor is provided the data
outputs from all devices are connected together, and internal
logic will enable the tri-state outputs when a device is ready to
output data i.e. DAV goes active. When data blocks are
overlapped it is possible that the output rate requirements will
limit the input sampling rate (see section on Multiple Device
Sampling Rates). Additional output processors will remove
this restriction, and the correct choice of multiple device
operating mode will optimise the sampling rates that can be
achieved with a given number of devices.
The synchronisation intervals, necessary to co-ordinate
input and output operations with the transform operation, lead,
in effect, to some uncertainty in the time needed to complete
a transform. Thus a particular device in a multiple device
system can effectively complete a transform in less system
clock periods than another device in the same system. To
prevent one device turning on its output bus before the
previous one has finished, it is either necessary to use a faster
output rate than would otherwise be required, or to use the
inverted DAV output from one device to drive the DEN input of
the next. The latter option allows DIS and DOS to be con-
nected together, and ensures that the second device will not
output data until the first device has finished.
This method of driving the DEN input from the inverted
DAV output from a previous device requires a change to the
single device DAV and DEN operation. If DEN is active at the
end of a transform in a multiple device system, the DAV output
will go active when the output circuit has been primed by the
DOS strobes. This operation is identical to that provided for a
single device system, and is transparent to the user as long as
DEN and DOS are active . If DEN is not active, however, the
DAV output will not asynchronously go active as happens in
a single device system. Instead DAV will only go active when
DEN eventually goes active. Since DEN is the inverted DAV
output from a previous device, it is thus never possible for two
devices to be actively outputting data. The DAV active going
edge remains synchronised to the DOS strobe since the DEN
input will only go active when a previous DAV goes in-active.
A further change to the output circuitry ensures that the output
buffer is primed even though DEN is not active. The first word,
however, only progresses as far as the final output latch. The
output bus is not enabled, and address increments do not
DEF
DIS / DOS
INTERNAL
START
INEN A
LFLG A
DAV A
INEN B
LFLG B
DAV B
INEN C
LFLG C
DAV C
LOAD A1
TRANSFORM A1
DUMP A
LOAD B1
TRANS
LOAD C1
TRANSFORM C1
Fig 10. Three Device System with Separate Load, Transform, and Dump Operations
13