PDSP16510A Datasheet, PDF (21/23 Pages) Mitel Networks Corporation – Stand Alone FFT Processor

PDSP16510A
ABSOLUTE MAXIMUM RATINGS [See Notes]
Supply voltage Vcc
-0.5V to 7.0V
Input voltage V_IN
-0.5V to Vcc + 0.5V
Output voltage V_OUT
-0.5V to Vcc + 0.5V
Clamp diode current per pin I_K (see note 2)
18mA
Static discharge voltage (HMB)
500V
Storage temperature T_S
Junction Temperature, Commercial
-65°C to 150°C
100°C
Junction temperature, Industrial
115°C
Junction Temperature, Military
155°C
Package power dissipation
5000mW
NOTES ON MAXIMUM RATINGS
Test
Waveform - measurement level
Delay from output
V_H
0.5V
high to output
high impedance
Delay from output
low to output
high impedance
V_L
0.5V
Delay from output _1.5V
high impedance to
0.5V
output low
1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceeded,
only one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended
periods may affect device reliablity.
4. Current is defined as positive into the device.
ELECTRICAL CHARACTERISTICS
Operating Conditions (unless otherwise state)
Delay from output
high impedance to
output high
1.5V
0.5V
V_H - Voltage reached wh en output driven hig
V_L - Voltage reached wh en output driven low
PDSP16510A C0 Tamb = 0 C to + 70°C. Vcc = 5.0v ± 5%
PDSP16510A B0 Tamb = -40 C to + 85°C. Vcc = 5.0v ± 10%
PDSP16510A A0 Tamb = -55 C to +125°C. Vcc = 5.0v ± 10%
Characteristic
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output S/C current
Symbol
V_OH
V_OL
V
IH
V_IL
I_IN
C_IN
I_OZ
I_SC
Value
Min. Typ. Max.
2.4
-
-
0.4
2.0
-
-
0.8
-10
+10
10
-50
+50
10
300
Units Notes
V
I_OH = 4mA
V
I_OL = -4mA
V SCLK, DIS, DOS, DEN need 3V
V DEN needs 0.7V max
µA
GND < V_IN < V_CC
pF
µA
GND < V_OUT < V_CC
mA V_CC = Max
SWITCHING CHARACTERISTICS
Characteristic
Clock Frequency ( MHz )
Clock High Period ( ns )
Clock Low Period ( ns )
Max DOS, DIS Frequency
Symbol
Ø
T_CH
T_CL
Ø_D
Min
DC
13
10
Max
40
FØ
Max DIS Frequency
Ø_D
Ø
Max DOS Frequency
Ø_D
Ø
Conditions
Max Ø high time is 1msec
Less than 1024 points or Mult Dev Mode 1
Note F =
4
6 + 0.001ØT
CL
1024 points or Mult Dev Modes 2 and 3
SCLK to DIS/DOS RELATIONSHIP
Both DIS and DOS must be synchronous to SCLK. Ideally they should both be produced from SCLK, in which case the
SCLK rising edge would either be first or coincident with the DIS and DOS rising edges.
In any event, the rising edge of SCLK must not fall between 2ns and 10ns after the rising edge of either DIS or DOS
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