PDSP16510A Datasheet, PDF (11/23 Pages) Mitel Networks Corporation – Stand Alone FFT Processor

PDSP16510A
In a single device system, performing non overlapped
transforms on data from a SINGLE source, only the Real input
pins are used, and the Imaginary inputs are redundant except
when configuring the device. By setting Control Register Bits
8:6 to 101, however, it is possible for a single device to accept
data from two independent sources using the real and imagi-
nary inputs. Maximum sampling rates will then only be half
those possible when a single source is used, if no incoming
data is to remain un-processed. With two sources a transform
must be completed in the time to load parallel blocks, other-
wise incoming data will be lost. With one source a transform
need not be finished until two data blocks have been acquired.
In this dual input mode results from data on the real inputs
always precede those from the imaginary inputs.
If block overlapping is needed, it is always necessary to load
pairs of data blocks simultaneously, using both the real and
imaginary inputs. With dual sources of data this presents no
problem, and Control Bits 8:6 should be set to 110 or 111 for
the relevant amount of overlapping. If data is from a single
source an external FIFO is needed to provide a simple delay
for a block of data. Decodes 001 through 100 from Control Bits
8:6 must be used to select the required overlap.
The output of the FIFO must provide data for the real
inputs. Continuous inputs can still be accepted, and each
block will initially occur on the imaginary inputs, and then occur
again on the real inputs as an output from the FIFO. The data
output sequence will consist of the results from a pair of inputs,
followed by the results obtained after the required overlap.
Thus with 50% overlapping the sequence is 1 & 2 followed by
1.5 & 2.5 followed by 3 & 4 followed by 3.5 & 4.5 etc., where
1 2 3 4 are the sequential inputs to the external FIFO, 1.5 is the
overlap between 1 & 2, and 2.5 is the overlap between 2 & 3.
When eight simultaneous 64 point transforms are per-
formed, the sampling rates given in Table 5 assume that data
is from a common source. The data outputs will be in the
correct sequence from 1 to 8, corresponding to inputs 1
through 8 in normal order from a single source. When data is
from two sources the sampling rates will be halved, and the
output sequence will be 1A 1B 2A 2B 3A 3B 4A 4B, where A
and B are the dual simultaneous sources on the real and
imaginary inputs respectively. If data block overlapping is
used in either of the above cases, the eight outputs will be
followed by results from the same basic eight blocks but time
displaced to give the required overlap. If more than two
sources are to be handled the user must provide appropriate
buffering and multiplexing, and the sampling rates must be
proportionally reduced.
When two 1024 point transforms are performed with a
single device, on data from a single source, the input buffer
must be arranged to acquire two blocks before initialising a
transfer to the device. In order to improve the maximum
sampling rates possible, data should be read simultaneously
from each half of the buffer, and loaded into the real and
imaginary inputs. This halves the transfer time from the buffer
to the device, but requires the device to expect dual inputs.
Configuration
Clock Periods
16 X 16PT
4 X 64PT
256PT
1024PT
8 X 64PT
2 X 256PT
2 X 1024PT
COMP
COMP
COMP
COMP
REAL
REAL
REAL
420
624
816
3907
816
1032
4699
Table 4. Computation Times in Clock Periods
Thus if block overlapping is not needed Control Register Bits
8:6 should be set to 101.
This fast transfer mode is supported by a special option
on the PDSP16540 Bucket Buffer. It will acquire two 1024
point non overlapping blocks using the sampling clock, and
then transfer the results to the FFT processor at the full system
clock rate. Figure 8 shows the system arrangement. It does
not support block overlapping.
With 1024 point transforms all block overlaps are handled
by the buffer logic, and not by the internal RAM, but the device
must still be programmed to expect the required overlap if the
external buffer makes use of the in-active LFLG edge to mark
the overlap point. To achieve the performance given in Table
5 with 50% overlaps, the buffer must provide sufficient storage
for at least 2.5 data blocks. With 75% overlaps it must provide
storage for 2.75 blocks. This extra storage allows transfers
between devices to be only needed when a complete new
block has been acquired for 50% overlaps, and when half a
new block has been acquired for 75% overlaps.If storage is
restricted to two data blocks, only half the sampling rates given
will be possible. Transfers between devices must then occur
when a half or a quarter of a new block has been acquired.
Since the minimum time between transfers must be no less
than the transform time itself, the sampling rates must be
proportionally reduced to prevent loss of data.
SINGLE DEVICE SAMPLING RATES
In a single device system the maximum sampling rate is
dependent on the transform size, the data overlap, and
whether real or complex data is applied. Table 4 gives the
times taken to complete the transforms for the various block
sizes, which include an allowance for synchronisation be-
tween the DIS strobe and the system clock. If continuous data
is to be transformed, the time to acquire a new block of data
(or partial block with overlapping) must be at least equal to
these transform times. Load and dump times must also be
added in the 1024 modes. For non continuous transforms the
peak rate is limited by the system clock rate and the factor , F,
16 X 16 COMPLEX
0% 50% 75%
4 X 64 COMPLEX
0% 50% 75%
256 COMPLEX
0% 50% 75%
1024 COMPLEX
0% 50% 75%
8 X 64 REAL
0% 50% 75%
2 X 256 REAL
0% 50% 75%
2 X 1024 REAL
0% 50% 75%
23.9 -
-
16.1 8.0 4.0 12.3 6.1 3.0
6.8 3.4 1.7 24.6 12.3 6.1 19.5 9.7 4.3 12.1 6.0 3.0
Table 5 :
Guide to MAX Sampling rates (in MHz) possible from a single device system.
SCLK is 40 MHz. Where sampling rate is asynchronous to SCLK, a PDSP16540 (or similar) is assumed on the input.
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