ZL50015_06 Datasheet, PDF (74/122 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch with Stratum 4E DPLL

ZL50015
Data Sheet
External Read Only Address: 0069_H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R3
R3
R3
R3
R2
R2
R2
R2
R1
R1
R1
R1
R0
R0
R0
R0
FML FMU
FL
FU
FML FMU
FL
FU
FML FMU
FL
FU
FML FMU
FL
FU
Bit
Name
Description
15
R3FML Reference 3 Multi-period Lower Limit Fail Bit
f the device sets this bit to high, the input REF3 fails the multi-period lower limit check.
(See Table 12, “Multi-Period Hysteresis Limits” on page 45)
14
R3FMU Reference 3 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the multi-period upper limit
check. (See Table 12, “Multi-Period Hysteresis Limits” on page 45)
13
R3FL Reference 3 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period lower limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
12
R3FU Reference 3 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF3 fails the single-period upper limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
11
R2FML Reference 2 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period lower limit check.
(See Table 12, “Multi-Period Hysteresis Limits” on page 45)
10
R2FMU Reference 2 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the multi-period upper limit
check. (See Table 12, “Multi-Period Hysteresis Limits” on page 45)
9
R2FL Reference 2 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period lower limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
8
R2FU Reference 2 Single Period Upper Limit Fail Bit
If the device sets this bit to high, the input REF2 fails the single-period upper limit
check.(see Table 11, “Values for Single Period Limits” on page 45)
7
R1FML Reference 1 Multi-period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period lower limit check.
(See Table 12, “Multi-Period Hysteresis Limits” on page 45)
6
R1FMU Reference 1 Multi-period Upper Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the multi-period upper limit
check. (See Table 12, “Multi-Period Hysteresis Limits” on page 45)
5
R1FL Reference 1 Single Period Lower Limit Fail Bit
If the device sets this bit to high, the input REF1 fails the single-period lower limit
check. (See Table 11, “Values for Single Period Limits” on page 45)
Table 39 - Reference Failure Status Register (RSR) Bits - Read Only
74
Zarlink Semiconductor Inc.