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ZL50015_06 Datasheet, PDF (109/122 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch with Stratum 4E DPLL
ZL50015
Data Sheet
FPo1/FPo3
CKo1/CKo3
tFPW1
tFODF1
tCKP1
tCKH1
Output Frame Boundary
tFODR1
tCKL1
tfCK1
VCT
trCK1
VCT
Figure 43 - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing Diagram
AC Electrical Characteristics† - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Master Mode, Divided Slave Mode, or
Multiplied Slave Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min. Typ.‡ Max. Units
Notes
1 FPo1 Output Pulse Width
2 FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
tFPW1
tFODF1
117 122 127 ns
56
66 ns
3 FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR1
56
66 ns
4 CKo1 Output Clock Period
tCKP1
117 122 127 ns
5 CKo1 Output High Time
tCKH1
56
66 ns
6 CKo1 Output Low Time
tCKL1
56
66 ns
7 CKo1 Output Rise/Fall Time
trCK1, tfCK1
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
CL = 30 pF
CL = 30 pF
AC Electrical Characteristics† - FPo1 and CKo1 or FPo3 and CKo3 (8.192 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min. Typ.‡ Max. Units
Notes
1 FPo1 Output Pulse Width
2 FPo1 Output Delay from the FPo1 falling edge
to the output frame boundary
tFPW1
tFODF1
106 122 127 ns
56
66 ns
3 FPo1 Output Delay from the output frame
boundary to the FPo1 rising edge
tFODR1
46
66 ns
4 CKo1 Output Clock Period
tCKP1
106 122 148 ns
5 CKo1 Output High Time
tCKH1
46
87 ns
6 CKo1 Output Low Time
tCKL1
46
66 ns
7 CKo1 Output Rise/Fall Time
trCK1, tfCK1
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
CL = 30 pF
CL = 30 pF
109
Zarlink Semiconductor Inc.