ZL50015_06 Datasheet, PDF (111/122 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch with Stratum 4E DPLL

ZL50015
Data Sheet
FPo3
CKo3
t_FPW3
t_FODF3
t_CKP3
t_CKH3
Output Frame Boundary
t_FODR3
t_CKL3
t_fCK3
V_CT
t_rCK3
V_CT
Figure 45 - FPo3 and CKo3 (32.768 MHz) Timing Diagram
AC Electrical Characteristics^† - FPo3 and CKo3 (32.768 MHz) Timing (Master Mode, Divided Slave Mode, or Multiplied Slave
Mode with less than 10 ns of Cycle to Cycle Variation on CKi)
Characteristic
Sym.
Min. Typ.^‡ Max. Units
Notes
1 FPo3 Output Pulse Width
2 FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
t_FPW3
t_FODF3
27 30.5 34 ns
10
18 ns
C_L = 30 pF
3 FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
t_FODR3
12
21 ns
4 CKo3 Output Clock Period
5 CKo3 Output High Time
t_CKP3
t_CKH3
27 30.5 34 ns
12
19
ns
C_L = 30 pF
6 CKo3 Output Low Time
t_CKL3
12
19 ns
7 CKo3 Output Rise/Fall Time
t_rCK3, t_fCK3
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics^† - FPo3 and CKo3 (32.768 MHz) Timing (Multiplied Slave Mode with more than
10 ns of Cycle to Cycle Variation on CKi
Characteristic
Sym.
Min. Typ.^‡ Max. Units
Notes
1 FPo3 Output Pulse Width
2 FPo3 Output Delay from the FPo3 falling edge
to the output frame boundary
t_FPW3
t_FODF3
27 30.5 34 ns
12
19 ns
C_L = 30 pF
3 FPo3 Output Delay from the output frame
boundary to the FPo3 rising edge
t_FODR3
12
19 ns
4 CKo3 Output Clock Period
5 CKo3 Output High Time
t_CKP3
t_CKH3
17 30.5 44 ns
5
29
ns
C_L = 30 pF
6 CKo3 Output Low Time
t_CKL3
12
18 ns
7 CKo3 Output Rise/Fall Time
t_rCK3, t_fCK3
5
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
111
Zarlink Semiconductor Inc.