ZL50018 Datasheet, PDF (73/136 Pages) Zarlink Semiconductor Inc – 2 K Digital Switch with Enhanced Stratum 3 DPLL

ZL50018
Data Sheet
External Read/Write Address: 0049_H
Reset Value: 099F_H (see Note)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL SRL
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
15 - 13 Unused Reserved. In normal functional mode, these bits MUST be set to zero.
12 - 0
SRL12 - 0 Slew Rate Limit Bits: The binary value of these bits defines the maximum rate of DPLL
phase change (phase slope), where the phase represents difference between the input
reference and output feedback clock. Defined in same units as CFN (unsigned).
Note: The default value is ±56 ppm (’h099F/CFN = 56 ppm).
Table 38 - Slew Rate Limit Register (SRLR) Bits
External Read/Write Address: 004A_H
Reset Value: 0002_H (see Note)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
BLM FLF_ FLC
FLC
FLC
FLC
FFL
FFL
FFL
FFL
LPF
LPF
LPF
LPF
QS
3
2
1
0
3
2
1
0
3
2
1
0
Bit
15 - 14
13
12
11 - 8
Name
Unused
BLM
FLF_QS
FLC3 - 0
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
Bypass Limiter Bit: When this bit is high, the DPLL slew rate limiter is bypassed
(ignored). In combination with FLF_QS, FLC3 - 0, FFL3 - 0 and LPF3 - 0 bits, causes fast
locking of the DPLL output clocks to the selected reference.
When this bit is low, the DPLL performs normal lock following the slew rate limit defined
in the slew rate limit register (SRLR).
Fast Lock Frequency Quick Stabilization Bit: This bit is used to control speed of
internal frequency stabilization.
When this bit is high, the DPLL internal frequency will quickly stabilize to the appropriate
value, allowing very fast storage of holdover frequency value.
When this bit is low, the internal frequency value will be reached over normal locking time
(i.e. <100 seconds), and some extra jitter on output clocks can be expected.
It is recommended to set this bit if fast locking functionality is desired.
When the BLM bit is low, this bit is ignored.
Fast Lock Control Bits: Value of these bits (unsigned) control stability of frequency
when FFL3 - 0 bits of this register are used. Larger values result in faster locking and are
recommended for reference clocks with small jitter, while smaller values are
recommended for references with presence of significant jitter.
Table 39 - Bandwidth Control Register (BWCR) Bits
73
Zarlink Semiconductor Inc.