ZL50018 Datasheet, PDF (101/136 Pages) Zarlink Semiconductor Inc – 2 K Digital Switch with Enhanced Stratum 3 DPLL

ZL50018
Data Sheet
24.2 Connection Memory Low (CM_L) Bit Assignment
When the CMM bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal
channel-switching. The connection memory low bit assignment for the channel transmission mode is shown in
Table 69 on page 101.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UA V/C SSA SSA SSA SSA SSA SCA SCA SCA SCA SCA SCA SCA SCA CMM
EN
4
3
2
1
0
7
6
5
4
3
2
1
0
=0
Bit
Name
Description
15
UAEN Conversion between µ-law and A-law Enable
When this bit is low, normal switch without µ-law/A-law conversion. Connec-
tion memory high will be ignored.
When this bit is high, switch with µ-law/A-law conversion, and connection
memory high controls the conversion method.
14
V/C Variable/Constant Delay Control
When this bit is low, the output data for this channel will be taken from con-
stant delay memory.
When this bit is set to high, the output data for this channel will be taken from
variable delay memory. Note that VAREN must be set in Control Register
first.
13 - 9 SSA4 - 0 Source Stream Address
The binary value of these 5 bits represents the input stream number.
8 - 1 SCA7 - 0 Source Channel Address
The binary value of these 8 bits represents the input channel number.
0 CMM = 0 Connection Memory Mode = 0
If this is low, the connection memory is in the normal switching mode. Bit13 -
1 are the source stream number and channel number.
Note: For proper µ-law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high.
Table 69 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0
101
Zarlink Semiconductor Inc.