ZL50018 Datasheet, PDF (1/136 Pages) Zarlink Semiconductor Inc – 2 K Digital Switch with Enhanced Stratum 3 DPLL

ZL50018
2 K Digital Switch with Enhanced
Stratum 3 DPLL
Data Sheet
Features
• 2048 channel x 2048 channel non-blocking digital
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and/or
16.384 Mbps
• 32 serial TDM input, 32 serial TDM output
streams
• Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 3
specifications
• Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
• DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
July 2005
Ordering Information
ZL50018GAC 256 Ball PBGA
ZL50018QCC 256 Lead LQFP
-40°C to +85°C
Trays
Trays
• Programmable key DPLL parameters (filter corner
frequency, locking range, auto-holdover
hysteresis range, phase slope, lock detector
range)
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
• Output streams can be configured as bi-
directional for connection to backplanes
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
REF0
REF1
REF2
REF3
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
OSC_EN
V_{DD_CORE}
V_{DD_IO}
V_{DD_COREA} V_{DD_IOA}
V_SS
RESET
ODE
S/P Converter
Data Memory
P/S Converter
Input Timing
DPLL
Connection Memory
Output HiZ
Control
Output Timing
OSC
Internal Registers &
Microprocessor Interface
Test Port
STio[31:0]
STOHZ[15:0]
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
Figure 1 - ZL50018 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.