PDSP16515A Datasheet, PDF (6/25 Pages) Mitel Networks Corporation – Stand Alone FFT Processor

PDSP16515A
subsequent passes a Control Register Bit allows the user to
continue to select these 18 bits, or instead to use the 18 most
significant bits. The latter option is equivalent to a 3 bit word
growth. The 2 or 3 bit word growth option applies to ALL
subsequent passes and is not a per pass option.
If the 2 bit option is selected there is a possibility of overflow
occurring in one of the passes. The prediction of overflow is
mathematically difficult, and only occurs with specific complex
square waves. Scaling down the inputs cannot be guaranteed
to prevent overflow because of the block floating point shifting
scheme, which is discussed later. Overflow can NEVER occur
if the 3 bit option is chosen, but at the expense of worse
dynamic range.
When overflow does occur a flag is raised which can be read
by the user ( see later discussion on scale tag bits ), and the
results ignored. In addition all frequency bins are forced to
zero to prevent any erroneous system response.
Even with only 2 bit word growth poor dynamic range can
result and becomes worse when the incoming data does not
fully occupy all the bits in the word. These problems are
overcome in the PDSP16515A, however, by a block floating
point scheme which compensates for any unnecessary word
growth.
During each pass the number of sign bits in the largest result
is recorded. Before the next pass, data is shifted left [multiplied
by 2], once for every extra sign bit in this recorded sample. At
least one component in the block then fully occupies the 18 bit
word, and maximum data accuracy is preserved
Up to four shifts are possible before every pass after the first,
with a total of fifteen for the complete transform. At the end of
the transform the number of left shifts that have occurred is
indicated on S3:0. Lack of pins prevents a separate output
being available to indicate that overflow has occurred in the 2
bit word growth option. For this reason the maximum number
of compensating left shifts in this mode is restricted to 14.
State 15 is then used to indicate that overflow has occurred.
The first step in the butterfly calculation multiplies 18 bit data
values with 16 bit sine/cosine values, to give 18 bit results.
WORKSPACE
A
INPUT
DATA
LOAD
WORKSPACE
B
TRANS-
FORM
FFT
DATA PATH
O/P
BUFFER
LOAD IN
LAST PASS
Figure. 4. RAM Organization with 256 Data
Points
6
INPUT
DATA
TRANS-
FORM
WORKSPACE
LOAD
FFT
DATA PATH
OUTPUT
Figure 5. RAM Organization with 1024 Point
Transforms
This increased word length preserves accuracy through the
following adder network, and has been shown through
simulations to be an optimum size for transform sizes up to
1024 points. This is particularly true when the input data is
restricted to below 16 bits, as is necessary with practical A/D
converters with very high sampling rates. The bottom bit of this
18 bit word is forced to logical one and as such is a
compromise between truncation and true rounding. It gives a
lower noise floor in the outputs compared to simple truncation.
To prevent any possibility of overflow during the butterfly
calculation the word length is allowed to grow by one bit
through each of the three adders. The least significant bit is
always discarded in the first two adders . Eighteen bits arethen
chosen from the final adder in the manner discussed earlier,
and the number of sign bits in the largest result recorded for
use in the following pass.
Fig. 3 shows one of the four internal data paths which can
compute a radix-4 butterfly in twelve system clock cycles. This
equates to completing the butterfly in 3 cycles for the complete
device.
Data Transfers
The data transfer mechanism to and from the internal RAM
has been designed for use in a wide variety of applications.
The provision of an independent input strobe (DIS), allows
data to be loaded without the need for additional external
buffering. An independent output strobe (DOS) is also
provided. DIS and DOS can thus be tied together, this being
particularly useful when the device is performing the inverse
transform back to the time domain. Transfer of data occurs
internally from DIS to SCLK, so although thay can be of
different frequencies, they must be synchronous to each
other. In the same way transfer of data also occurs from SCLK
to DOS, so while DOS can also be independent of SCLK it
must also be synchronous to it. Inputs and outputs are both
supported by flag and enabling signals which allow transfers
to be properly co-ordinated with the internal transform
operation.
In many applications the DIS and DOS inputs can be tied
together and fed by the sampling clock. If the output rate must
be higher than the input rate, as with multiple devices
supporting overlapped data samples, both strobes can still be
connected together. The clock supplied should then be twice
or four times the sampling clock, and an internal divider can be
used to provide the correctly reduced input rate. The provision
of a separate DOS pin does, however, allow the output rate to
be different to the input rate, and therefore faster than strictly
needed. Further output processing at higher rates is then
possible if this is advantageous to system requirements.