PDSP16515A Datasheet, PDF (24/25 Pages) Mitel Networks Corporation – Stand Alone FFT Processor

PDSP16515A
Absolute Maximum Ratings [See Notes]
Supply voltage Vcc
-0.5V to 7.0V
Input voltage V_IN
-0.5V to Vcc + 0.5V
Output voltage V_OUT
-0.5V to Vcc + 0.5V
Clamp diode current per pin I_K (see note 2)
18mA
Static discharge voltage (HMB)
500V
Storage temperature T_S
Junction Temperature, Commercial
-65°C to 150°C
100°C
Junction temperature, Industrial
115°C
Junction Temperature, Military
155°C
Package power dissipation
5000mW
Notes on Maximum Ratings
1. Exceeding these ratings may cause permanent damage.
Functional operation under these conditions is not implied.
2. Maximum dissipation or 1 second should not be exceeded,
only one output to be tested at any one time.
3. Exposure to absolute maximum ratings for extended
periods may affect device reliablity.
4. Current is defined as positive into the device.
Electrical Characterisitcs
Operating Conditions (unless otherwise state)
Test
Waveform - measurement
Delay from output
V_H
high to output
high impedance
0.5V
Delay from output
low to output
high impedance
V_L
0.5V
Delay from output
high impedance to
output low
1.5V
0.5V
Delay from output
high impedance to
output high
1.5V
0.5V
V_H - Voltage reached when output driven high
V_L - Voltage reached when output driven low
PDSP16515A C0 Tamb = 0 C to + 70°C. Vcc = 5.0v ± 5%
PDSP16515A B0 Tamb = -40 C to + 85°C. Vcc = 5.0v ± 10%
PDSP16515A A0 Tamb = -55 C to +125°C. Vcc = 5.0v ± 10%
Characteristic
Symbol
Value
Min. Typ. Max.
Units Notes
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
Input capacitance
Output leakage current
Output S/C current
V_OH
2.4
-
V
I_OH = 4mA
V
OL
-
0.4
V
I = -4mA
OL
V_IH
2.0
-
V SCLK, DIS, DOS, DEN need 3V
V_IL
-
0.8
V DEN needs 0.7V max
I
IN
-10
+10
µA
GND < V < V
IN
CC
C_IN
10
pF
I_OZ
-50
+50
µA
GND < V_OUT < V_CC
I
SC
10
300
mA
V = Max
CC
Switching Characteristics
Characteristic
Clock Frequency (MHz)
Clock High Period (ns)
Clcok low Period (ns)
Max DOS, DIS Frequency
Comm
Symbol Min
∅
DC
T
10
CH
T_CL
9
∅_D
Ind
Max
45
F_âˆ
Max DIS Frequency
∅_D
45
Max DOS Frequency
∅_D
45
Military
Min Max
DC
40
11
10
F_âˆ
40
40
Conditions
Max ∅ high time is 1msec
Less than 1024 points or Multi Dev Mode 1
Note F =
4
6 + 0.001∅T_CL
1024 points or Multi Dev Modes 2 and 3
D15, DOS must be driven from ∅
SCLK to DIS/DOS RELATIONSHIP
Both DIS and DOS must be synchronous to SCLK. Ideally they should both be produced from SCLK, in which case the
SCLK rising edge would either be first or coincident with the DIS and DOS rising edges.
In any event, the rising edge of SCLK must not fall between 2ns and 10ns after the rising edge of either DIS or DOS
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