ZL50016_06 Datasheet, PDF (57/81 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch

ZL50016
Data Sheet
The ICL, the OCL bits and V/D bit only have an effect on PCM code translations for constant delay connections,
variable delay connections and per-channel message mode.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
V/D ICL ICL OCL OCL
1
0
1
0
Bit
15 - 5
4
3-2
Name
Description
Unused Reserved
In normal functional mode, these bits MUST be set to zero.
V/D Voice/Data Control
When this bit is low, the corresponding channel is for voice.
When this bit is high, the corresponding channel is for data.
ICL1 - 0 Input Coding Law.
ICL1-0
00
01
10
11
Input Coding Law
For Voice (V/D bit = 0)
For Data (V/D bit = 1)
CCITT.ITU A-law
CCITT.ITU µ-law
A-law w/o ABI
µ-law w/o Magnitude
Inversion
No code
ABI
Inverted ABI
All Bits Inverted
1-0
OCL1 - 0 Output Coding Law
OCL1-0
00
01
10
11
Output Coding Law
For Voice (V/D bit = 0) For Data (V/D bit = 1)
CCITT.ITU A-law
CCITT.ITU µ-law
A-law w/o ABI
µ-law w/o Magnitude
Inversion
No code
ABI
Inverted ABI
All Bits Inverted
Note 1: For proper µ-law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high.
Note 2: Refer to G.711 standard for detail information of different laws.
Table 32 - Connection Memory High (CM_H) Bit Assignment
57
Zarlink Semiconductor Inc.