ZL50016_06 Datasheet, PDF (1/81 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch

ZL50016
Enhanced 1 K Digital Switch
Data Sheet
Features
• 1024 channel x 1024 channel non-blocking digital
Time Division Multiplex (TDM) switch at
4.096 Mbps, 8.192 Mbps and 16.384 Mbps or
using a combination of ports running at
2.048 Mbps, 4.096 Mbps, 8.192 Mbps and
16.384 Mbps
• 16 serial TDM input, 16 serial TDM output
streams
• Output streams can be configured as bi-
directional for connection to backplanes
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
• Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps,
8.192 Mbps or 16.384 Mbps. Input and output
data rates can differ
• Per-stream high impedance control outputs
(STOHZ) for 8 output streams
November 2006
Ordering Information
ZL50016GAC
ZL50016QCC
ZL50015QCG1
ZL50016GAG2
256 Ball PBGA
256 Lead LQFP
256 Lead LQFP*
256 Ball PBGA**
Trays
Trays
Trays, Bake &
Drypack
Trays, Bake &
Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Per-stream input bit delay with flexible sampling
point selection
• Per-stream output bit and fractional bit
advancement
• Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses:61 ns, 122 ns, 244 ns
• Four frame pulse and four reference clock outputs
V_{DD_CORE} V_{DD_IO} V_{DD_COREA} V_{DD_IOA} V_SS RESET
ODE
STi[15:0]
FPi
CKi
MODE_4M0
MODE_4M1
S/P Converter
Input Timing
Data Memory
Connection Memory
Internal Registers &
Microprocessor Interface
P/S Converter
Output HiZ
Control
Output Timing
Test Port
STio[15:0]
STOHZ[7:0]
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Figure 1 - ZL50016 Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.