ZL50016_06 Datasheet, PDF (15/81 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch

ZL50016
Data Sheet
PBGA Pin
Number
N12
LQFP Pin
Number
44
R11
40
N11
39
R12
42
K13, K15,
K14, J11,
J12, J13,
J15, H11,
J14, H12,
H13, H15,
G12, G13
M13
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
41
G2
211
Pin Name
DTA_RDY
CS
R/W_WR
DS_RD
A0 - 13
MOT_INTEL
RESET
Description
Data Transfer Acknowledgment_Ready (5 V-Tolerant
Three-state Output)
This active low output indicates that a data bus transfer is
complete for the Motorola interface. For the Intel interface, it
indicates a transfer is completed when this pin goes from low to
high. An external pull-up resistor MUST hold this pin at HIGH level
for the Motorola mode. An external pull-down resistor MUST hold
this pin at LOW level for the Intel mode.
Chip Select (5 V-Tolerant Input)
Active low input used by the Motorola or Intel microprocessor to
enable the microprocessor port access.
Read/Write_Write (5 V-Tolerant Input)
This input controls the direction of the data bus lines (D0 - 15)
during a microprocessor access. For the Motorola interface, this
pin is set high and low for the read and write access respectively.
For the Intel interface, a write access is indicated when this pin
goes low.
Data Strobe_Read (5 V-Tolerant Input)
This active low input works in conjunction with CS to enable the
microprocessor port read and write operations for the Motorola
interface. A read access is indicated when it goes low for the Intel
interface.
Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up)
This pin selects the Motorola or Intel microprocessor interface to
be connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin
is connected to ground, Intel interface should be used.
Device Reset (5 V-Tolerant Input with Internal Pull-up)
This input (active LOW) puts the device in its reset state that
disables the STio0 - 15 drivers and drives the STOHZ0 - 7 outputs
to high. It also preloads registers with default values and clears all
internal counters. To ensure proper reset action, the reset pin
must be low for longer than 1 µs. Upon releasing the reset signal
to the device, the first microprocessor access cannot take place
for at least 600 µs due to the time required to stabilize the device
from the power-down state. Refer to Section Section 13.2 on
page 32 for details.
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Zarlink Semiconductor Inc.