ZL50016_06 Datasheet, PDF (50/81 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch

ZL50016
Data Sheet
External Read/Write Address: 0120_H - 012F_H
Reset Value: 0000_H
15 14 13 12
11
10
9
0
0
0
0 STIN[n] STIN[n] STIN[n]
Q3C2
Q3C1
Q3C0
8
STIN[n]
Q2C2
7
STIN[n]
Q2C1
6
STIN[n]
Q2C0
5
STIN[n]
Q1C2
4
STIN[n]
Q1C1
3
STIN[n]
Q1C0
2
STIN[n]
Q0C2
1
STIN[n]
Q0C1
0
STIN[n]
Q0C0
Bit
5-3
2-0
Name
Description
STIN[n]Q1C2 - 0
Quadrant Frame 1 Control Bits
these three bits are used to control STi[n]’s quadrant frame 1, which is defined
as Ch8 to 15, Ch16 to 31, Ch32 to 63 and Ch64 to 127 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q1C
2-0
0xx
100
101
110
111
Operation
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
STIN[n]Q0C2 - 0
Quadrant Frame 0 Control Bits
These three bits are used to control STi[n]’s quadrant frame 0, which is defined
as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps,
4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively.
STIN[n]Q0C2-0
0xx
100
101
110
111
Operation
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
Note: [n] denotes input stream from 0 - 15.
Table 23 - Stream Input Quadrant Frame Register 0 - 15 (SIQFR0 - 15) Bits (continued)
50
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