MT90883 Datasheet, PDF (54/97 Pages) Zarlink Semiconductor Inc – TDM to Packet Processors

MT90880/1/2/3
Data Sheet
In the absence of a priority requirement, the weights should be set to the same value to allow equal access to
the bandwidth. For example, in option 4 all the weights should be set to 16, allocating 25 Mbs per queue.
Drop Thresholds
The MT9088x has the ability to restrict the amount of memory used by each queue. When the memory
utilisation reaches the limit, new packets are dropped. This limitation prevents a queue from increasing in size
to the point where the device runs out of memory, causing the whole device to crash and lose data. For
instance, this could potentially happen if an Ethernet link failed, causing a backlog of packets to build up in the
queues to that link.
The drop thresholds are programmed in units of granules, where a memory granule is a 128-byte block of data
(see the section “Granule Structure” on page 64). For the queues to the packet interface, the thresholds can be
set to between 0 and 1023 granules per queue. In addition, it is possible to set an overall threshold for the
maximum number of granules allowed in all the queues to the packet interface at any one time.
If required, it is possible to disable the packet dropping when the drop thresholds are exceeded, although this is
not normally recommended. Exceeding the drop threshold causes an interrupt to the control CPU to inform it of
the queue size violation, since this normally indicates some kind of error condition (e.g. an Ethernet link failure,
as described above).
6.5.2 Queues to PCI Interface
The MT9088x maintains four separate queues of packets waiting for transfer to the CPU. These are for packets
arriving over the network that either do not contain TDM data, or contain TDM data that needs processing by
some external resource on the PCI bus (e.g. a DSP). The packet classification process is capable of identifying
up to four different traffic classes, and can direct each of these traffic classes to a different queue. Unmatched
traffic is always sent to CPU queue 0.
Priority of CPU Queues
The internal DMA controller is used to transfer packets from the MT9088x's packet memory into the system
memory on the PCI bus (see the “DMA Controller” on page 71). While the CPU queues have no inherent priority
levels associated with them, in that the CPU can choose to service which queue it wants to first, there is a
priority level associated with the DMA transfer into system memory. The device uses strict priority order to
determine which queue gets serviced first, with queue 3 having the highest priority and queue 0 the lowest
priority. Therefore the DMA will only transfer packets in a given queue if all the higher priority queues are empty
or stalled (queues may be stalled if there is no free space in system memory for them to be transferred into).
Drop Thresholds
As with the queues to the packet interface, there are also drop thresholds associated with the queues to the PCI
interface. The drop thresholds are programmed in units of granules, and can be set to between 0 and 1023
granules per queue. Again, it is possible to disable packet dropping, although this is not normally
recommended. Exceeding the drop threshold causes an interrupt to the control CPU to inform it of the queue
size violation.
6.5.3 Queues to WAN Interface
The packet classifier identifies the packets arriving over the network that contain TDM data, and retrieves the
context ID from the two-byte context descriptor. A separate queue is provided for each context, and the
classifier forwards the packets to the appropriate queue. The WAN Transmit block reads packets from the end
of the queue at a regular rate, and re-formats the data for transmission over the WAN Access Interface or the
Local TDM interface. No priority is associated with these queues, since each WAN context is independent, and
does not compete for resource against the other contexts.
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