MT90883 Datasheet, PDF (14/97 Pages) Zarlink Semiconductor Inc – TDM to Packet Processors

MT90880/1/2/3
Data Sheet
Signal
LOC_STO [7:0]
c4ob
fp4ob
c8ob
fp8ob
c16ob
fp16ob
ode
I/O
Package Balls
Description
O L5 [7], L4 [6], K2 [5], L3 [4],
L2 [3], P4 [2], M2 [1], N3 [0]
Local TDM interface serial output
streams
Operate at 2.048, 4.096 and 8.192 Mbs
MT90880 variant only
O B8
TDM interface 4.096 MHz clock
All variants
O C8
8 KHz frame pulse for C4OB clock
All variants
O A7
TDM interface 8.192 MHz clock
All variants
O A6
8 KHz frame pulse for C8OB clock.
All variants
O B7
TDM interface 16.384 MHz clock
All variants
O D8
8 KHz frame pulse for C16OB clock.
All variants
I D A8
WAN and TDM serial output enable. High
to enable outputs, low for high
impedance.
All variants
Table 5 - Local TDM Interface (continued)
3.3 Packet Interfaces
3.3.1 MII Interfaces
Data for the MII packet switching is based on Specification IEEE Std 802.3u – 1995. The MII has separate
transmit and receive circuits, and consequently the characteristics are shown in the relevant tables.
All MII signals are 5 V tolerant.
All MII outputs are high impedance while S_RST is low.
Signal
m_mdc
m_mdio
MII Port A
m_mint0
m0_txd[3:0]
m0_txen
I/O
O AF9
IOU AC10
Package Balls
Description
MII management data clock.
Common for both MII ports.
MII management data I/O
Common for both MII ports; 2.5 MHz
I U AF6
O U AC8 [3], AF5 [2], AE6 [1], AD7 [0]
O U AD6
MII management interrupt for port A
Transmit data
Transmit enable
Table 6 - MII Interfaces
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